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參數(shù)資料
| 型號： | AD9833BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PDSO10 |
| 封裝： | ROHS COMPLAINT, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 210K |
| 代理商： | AD9833BRM |
AD9833
–
11
–
REV PrG
PRELIMINARY TECHNICAL DATA
The Frequency and Phase Resisters
The AD9833 contains 2 frequency registers and 2 phase
registers. These are described in Table 3 below.
Table 3. Frequency/Phase Registers
Register
Size
Description
FREQ0
28 Bits
Frequency Register 0. When the
FSELECT bit = 0, this register
defines the output frequency as a
fraction of the MCLK frequency.
Frequency Register 1. When the
FSELECT bit = 1, this register
defines the output frequency as a
fraction of the MCLK frequency.
Phase Offset Register 0. When the
PSELECT bit = 0, the contents of
this register are added to the output
of the phase accumulator.
Phase Offset Register 1. When the
PSELECT bit = 1, the contents of
this register are added to the output
of the phase accumulator.
FREQ1
28 Bits
PHASE0
12 Bits
PHASE1
12 Bits
The analog output from the AD9833 is
f
MCLK
/2
28
x FREQREG
where FREQREG is the value loaded into the selected
frequency register. This signal will be phase shifted by
2
π
/4096 x PHASEREG
where PHASEREG is the value contained in the selected
phase register.
The flow chart in Figure 8 shows the routine for writing
to the frequency and phase registers of the AD9833.
Writing to a Frequency Register:
When writing to a frequency register, bits D15 and D14
give the address of the frequency register.
Table 4. Frequency Register Bits
D15
D14
D13
D0
0
1
1
0
MSB
MSB
14 FREQ0 REG BITS
14 FREQ1 REG BITS
LSB
LSB
If the user wishes to alter the entire contents of a fre-
quency register, two consecutive writes to the same
address must be performed, as the frequency registers are
28 bits wide. The first write will contain the 14 LSBs
while the second write will contain the 14 MSBs. For this
mode of operation, the control bit B28 (D13) should be
set to 1. An example of a 28-bit write is shown in Table 5.
Table 5: Writing 3FFF0000 to FREQ0 REG
SDATA input
Result of input word
0010 0000 0000 0000
Control word write (D15, D14 = 00);
B28 (D13) = 1; HLB (D12) = X
FREQ0 REG write (D15, D14 = 01);
14 LSBs = 0000
FREQ0 REG write (D15, D14 = 01);
14 MSBs = 3FFF
0100 0000 0000 0000
0111 1111 1111 1111
In some applications, the user does not need to alter all 28
bits of the frequency register. With coarse tuning, only
the 14 MSBs are altered while with fine tuning, only the
14 LSBs are altered. By setting the control bit B28 (D13)
to 0, the 28-bit frequency register operates as 2 14-bit
registers, one containing the 14 MSBs and the other con-
taining the 14 LSBs. This means that the 14 MSBs of the
frequency word can be altered independent of the 14 LSBs
and vice versa. Bit HLB (D12) in the control register
identifies which 14 bits are being altered. Examples of this
are shown below.
Table 6: Writing 3FFF to the 14 LSBs of FREQ1 REG
SDATA input
Result of input word
0000 0000 0000 0000
Control word write (D15, D14 = 00);
B28 (D13) = 0; HLB (D12) = 0, i.e. LSBs
FREQ1 REG write (D15, D14 = 10);
14 LSBs = 3FFF
1011 1111 1111 1111
Table 7: Writing 3FFF to the 14 MSBs of FREQ0 REG
SDATA input
Result of Input word
0001 0000 0000 0000
Control word write (D15, D14 = 00);
B28 (D13) = 0; HLB (D12) = 1, i.e. MSBs
FREQ0 REG write (D15, D14 = 01);
14 MSBs = 3FFF
0111 1111 1111 1111
Writing to a Phase Register:
When writing to a phase register, bits D15 and D14 are
set to 11. Bit D13 identifies which phase register is being
loaded.
Table 8. Phase Register Bits
D15 D14
D13
D12
D11
D0
1
1
1
1
0
1
X
X
MSB
MSB
12 PHASE0 BITS
12 PHASE1 BITS
LSB
LSB
The RESET Function
The RESET function resets appropriate internal registers
to zero to provide an analog output of midscale. RESET
does not reset the phase, frequency or control registers.
When the AD9833 is powered up, the part should be re-
set. To reset the AD9833, set the RESET bit to 1. To
take the part out of reset, set the bit to 0. A signal will
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