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參數資料
| 型號： | AD9833BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PDSO10 |
| 封裝： | ROHS COMPLAINT, MO-187BA, MSOP-10 |
| 文件頁數： | 9/18頁 |
| 文件大小： | 210K |
| 代理商： | AD9833BRM |
AD9833
–
9
–
REV PrG
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION
Serial Interface
The AD9833 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing dia-
gram for this operation is given in Figure 3.
The FSYNC input is a level triggered input that acts as a
frame synchronisation and chip enable. Data can only be
transferred into the device when FSYNC is low. To start
the serial data transfer, FSYNC should be taken low, ob-
serving the minimum FSYNC to SCLK falling edge setup
time, t
7
. After FSYNC goes low, serial data will be shifted
into the device's input shift register on the falling edges of
SCLK for 16 clock pulses. FSYNC may be taken high
after the sixteenth falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time,
t
8
. Alternatively, FSYNC can be kept low for a multiple of
16 SCLK pulses, and then brought high at the end of the
data transfer. In this way, a continuous stream of 16 bit
words can be loaded while FSYNC is held low, FSYNC
only going high after the 16th SCLK falling edge of the
last word loaded.
The SCLK can be continuous or, alternatively, the SCLK
can idle high or low between write operations.
Powering up the AD9833
The flow chart in Figure 6 shows the operating routine for
the AD9833. When the AD9833 is powered up, the part
should be reset. This will reset appropriate internal regis-
ters to zero to provide an analog output of midscale. To
avoid spurious DAC outputs while the AD9833 is being
initialized, the RESET bit should be set to 1 until the part
is ready to begin generating an output. RESET does not
reset the phase, frequency or control registers. These reg-
isters will contain invalid data and, therefore, should be set
to a known value by the user. The RESET bit should then
be set to 0 to begin generating an output. A signal will
appear at the DAC output 7 MCLK cycles after RESET is
set to 0.
Latency
Associated with each asynchronous write operation in the
AD9833 is a latency. If a selected frequency/phase register
is loaded with a new word there is a delay of 7 to 8 MCLK
cycles before the analog output will change. (There is an
uncertainty of one MCLK cycle as it depends on the posi-
tion of the MCLK rising edge when the data is loaded into
the destination register.)
The Control Register
The AD9833 contains a 16-bit control register which sets
up the AD9833 as the user wishes to operate it. All control
bits, except MODE, are sampled on the internal negative
edge of MCLK.
Table 2, on the following page, describes the individual
bits of the control register. The different functions and the
various output options from the AD9833 are described in
more detail in the section following Table 2.
To inform the AD9833 that you wish to alter the contents
of the Control register, D15 and D14 must be set to '0' as
shown below.
Table 1. Control Register
D15
D14
D13
D0
0
0
CONTROL BITS
Figure 5. Function of Control Bits
SIN
ROM
(Low Power)
10-Bit DAC
VOUT
AD9833
Phase
Accumulator
(28 Bit)
1
DIV BY
2
MUX
0
DIGITAL
OUTPUT
(enable)
SLEEP12
SLEEP1
RESET
OPBITEN
DIV2
0
1
0
B28
DB12 FSELECT PSELECT
DB10
0
RESET
SLEEP1 SLEEP12
DB6
DB5
DB4
0
DB3
0
DB1
0
0
MODE + OPBITEN
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9833BRM-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Serial 10-Pin MSOP T/R 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR 10MSOP - Tape and Reel |
| AD9833BRM-REEL7 | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9833BRMZ | 功能描述:IC WAVEFORM GENERTR PROG 10-MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9833BRMZ | 制造商:Analog Devices 功能描述:WAVEFORM GENERATOR 9833 MSOP10 |
| AD9833BRMZ-REEL | 功能描述:IC WAVEFORM GEN PROG 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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