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參數(shù)資料
型號: AD9833BRM
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理外設
英文描述: +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS
中文描述: DSP-NUM CONTROLLED OSCILLATOR, PDSO10
封裝: ROHS COMPLAINT, MO-187BA, MSOP-10
文件頁數(shù): 15/18頁
文件大小: 210K
代理商: AD9833BRM
AD9833
15
REV PrG
PRELIMINARY TECHNICAL DATA
Figure 8. Data Writes
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface which allows
the part to interface directly with several microprocessors.
The device uses an external serial clock to write the data/
control information into the device. The serial clock can
have a frequency of 40 MHz maximum. The serial clock
can be continuous or, it can idle high or low between
write operations. When data/control information is being
written to the AD9833, FSYNC is taken low and is held
low while the 16 bits of data are being written into the
AD9833. The FSYNC signal frames the 16 bits of infor-
mation being loaded into the AD9833.
AD9833 to ADSP-21xx Interface
Figure 9 shows the serial interface between the AD9833
and the ADSP-21xx. The ADSP-21xx should be set up to
operate in the SPORT Transmit Alternate Framing Mode
(TFSW = 1). The ADSP-21xx is programmed through
the SPORT control register and should be configured as
follows:
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generate a frame sync for each write (TFSR = 1).
Transmission is initiated by writing a word to the Tx reg-
ister after the SPORT has been enabled. The data is
clocked out on each rising edge of the serial clock and
clocked into the AD9833 on the SCLK falling edge.
ADSP-2101/
ADSP-2103*
AD9833*
TFS
DT
SCLK
FSYNC
* ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
Figure 9. ADSP2101/ADSP2103 to AD9833 Interface
AD9833 to 68HC11/68L11 Interface
Figure 10 shows the serial interface between the AD9833
and the 68HC11/68L11 microcontroller. The
microcontroller is configured as the master by setting bit
MSTR in the SPCR to 1 and, this provides a serial clock
on SCK while the MOSI output drives the serial data line
SDATA. Since the microcontroller does not have a dedi-
cated frame sync pin, the FSYNC signal is derived from a
port line (PC7). The set up conditions for correct opera-
tion of the interface are as follows:
DATA WRITE
WRITE A FULL 28-BIT WORD
TO A FREQUENCY REGISTER
WRITE 14 MSBs OR LSBs
TO A FREQUENCY REGISTER
WRITE TO PHASE
REGISTER
(CONTROL REGISTER WRITE)
B28 (D13) = 1
WRITE 2 CONSECUTIVE
16-BIT WORDS
(See Table 5 for Example)
WRITE A 16-BIT WORD
(See Tables 6 & 7 for
examples)
(CONTROL REGISTER WRITE)
B28 (D13) = 0
HLB (D12) = 0 / 1
WRITE ANOTHER FULL
28 BITS TO A
FREQUENCY REGISTER
WRITE 14 MSBs OR LSBs
TO A
FREQUENCY REGISTER
(16 - Bit Write)
D15, D14 = 11
D13 = 0/1 (chooses the
phase register)
D12 = X
D11 ... D0 = Phase Data
WRITE TO ANOTHER
PHASE REGISTER
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
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相關代理商/技術參數(shù)
參數(shù)描述
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AD9833BRMZ-REEL 功能描述:IC WAVEFORM GEN PROG 10MSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率(位):10 b 主 fclk:25MHz 調(diào)節(jié)字寬(位):32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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