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參數(shù)資料
| 型號(hào)： | AD9845A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | 完整的12位30 MSPS的CCD信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 12/22頁(yè) |
| 文件大小： | 252K |
| 代理商： | AD9845A |
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REV. 0
AD9845A
–12–
0101...
0101...
0101...
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
2323...
2323...
2323...
HD
LINE 0
LINE 1
LINE 2
LINE m
LINE m
–
1
LINE 0
LINE 1
LINE 2
LINE m
LINE m
–
1
EVEN FIELD
ODD FIELD
VD
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA
GAIN
GAIN0
GAIN1
GAIN0
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323 ... (ODD).
GAIN3
GAIN2
GAINX
GAINX
3ns MIN
VD
3ns MIN
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
FRAME n
VD
HD
LINE 0
LINE 1
LINE 2
LINE m
0101...
1212...
0101...
LINE m
–
1
LINE 0
LINE 1
LINE 2
LINE m
0101...
1212...
0101...
LINE m
–
1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
FRAME n+1
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
GAIN0
GAIN1
GAIN0
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
GAIN2
GAINX
GAINX
GAIN1
3ns MIN
VD
3ns MIN
5 PIXEL MIN
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9845AJST | Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9846A | Complete 10-Bit 30 MSPS CCD Signal Processor |
| AD9846AJST | Complete 10-Bit 30 MSPS CCD Signal Processor |
| AD9847 | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| AD9847AKST | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9845AJST | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 30 MHZ AFE NO PXGA - Bulk |
| AD9845AJSTRL | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Tape and Reel |
| AD9845B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845BJST | 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Trays 制造商:Rochester Electronics LLC 功能描述: |
| AD9845BJSTRL | 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 30MHZ AFE NO PXGA - Tape and Reel |
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