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參數資料
| 型號： | AD9845A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | 完整的12位30 MSPS的CCD信號處理器 |
| 文件頁數： | 21/22頁 |
| 文件大小： | 252K |
| 代理商： | AD9845A |
REV. 0
AD9845A
–21–
Internal Power-On Reset Circuitry
After power-on, the AD9845A will automatically reset all inter-
nal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset opera-
tion is completed. Pin 43 (formerly RSTB on the AD984x non-A
products) is no longer used for the reset operation. Toggling Pin
43 in the AD9845A will have no effect.
Grounding and Decoupling Recommendations
As shown in Figure 33, a single ground plane is recommended
for the AD9845A. This ground plane should be as continuous
as possible, particularly around Pins 25 through 39. This will
ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins and
their respective ground pins. All decoupling capacitors should
be located as close as possible to the package pins. A single clean
power supply is recommended for the AD9845A, but a separate
digital driver supply may be used for DRVDD (Pin 13). DRVDD
should always be decoupled to DRVSS (Pin 14), which should
be connected to the analog ground plane. Advantages of using
a separate digital driver supply include using a lower voltage
(2.7 V) to match levels with a 2.7 V ASIC, reducing digital power
dissipation, and reducing potential noise coupling. If the digital
outputs (Pins 3–12) must drive a load larger than 20 pF, buffer-
ing is recommended to reduce digital code transition noise.
Alternatively, placing series resistors close to the digital out-
put pins may also help reduce noise.
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
37
48 47 46 45 44
39 38
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
(MSB) D11
AD9845A
S
S
S
N
S
R
T
D
D
V
V
C
D
D
D
D
D
H
P
C
S
S
C
V
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
3V
ANALOG SUPPLY
CCD SIGNAL
3V
ANALOG SUPPLY
12
DATA
OUTPUTS
3
SERIAL
INTERFACE
0.1 F
1.0 F
1.0 F
0.1 F
3V
ANALOG SUPPLY
8
CLOCK
INPUTS
0.1 F
0.1 F
3V
ANALOG SUPPLY
3V
DRIVER
SUPPLY
NC = NO CONNECT
Figure 33. Recommended Circuit Configuration for CCD-Mode
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9845AJST | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 30 MHZ AFE NO PXGA - Bulk |
| AD9845AJSTRL | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Tape and Reel |
| AD9845B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 30 MSPS CCD Signal Processor |
| AD9845BJST | 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Trays 制造商:Rochester Electronics LLC 功能描述: |
| AD9845BJSTRL | 制造商:Analog Devices 功能描述:CCD SGNL PROCESSOR 48LQFP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12 BIT 30MHZ AFE NO PXGA - Tape and Reel |
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