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參數資料
| 型號： | AD9845B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 30 MSPS CCD Signal Processor |
| 中文描述： | 完整的12位30 MSPS的CCD信號處理器 |
| 文件頁數： | 18/24頁 |
| 文件大小： | 441K |
| 代理商： | AD9845B |
REV. A
–18–
AD9845B
R
R
Gb
Gb
Gr
Gr
B
B
CCD: PROGRESSIVE BAYER
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
R
R
Gr
Gr
Gb
Gb
B
B
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 26. CCD Color Filter Example: Progressive Scan
LINE0
GAIN0, GAIN1, GAIN0, GAIN1...
R
R
Gr
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN0, GAIN1, GAIN0, GAIN1...
Gb
Gb
B
B
LINE0
GAIN2, GAIN3, GAIN2, GAIN3...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN2, GAIN3, GAIN2, GAIN3...
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
ODD FIELD
Gb
Gb
B
B
Gb
Gb
B
B
Gb
Gb
B
B
R
R
Gr
Gr
R
R
Gr
Gr
R
R
Gr
Gr
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
selected mode should be used with this type of CCD (see
Figure 27). The color steering performs the proper multiplexing
of the R, G, and B gain values (loaded into the
PxGA
gain regis-
ters) and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the
PxGA
Timing section. The
PxGA
gain for each of the four
channels is variable from –2.5 dB to +9.5 dB, controlled in 64
steps through the serial interface. The
PxGA
gain curve is
shown in Figure 28.
PxGA
GAIN REGISTER CODE
8
32
P
40
48
58
0
8
16
24
31
6
4
2
0
–2
–4
(011111)
(100000)
10
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with approximately 4 dB from the
PxGA
stage, the
total gain range for the AD9845B is 6 dB to 40 dB. The mini-
mum gain of 6 dB is needed to match a 1 V input signal with
the ADC full-scale range of 2 V. When compared to 1 V full-
scale systems (such as ADI’s AD9803), the equivalent gain
range is 0 dB to 34 dB.
The VGA gain curve follows a “linear-in-dB” shape. The exact
VGA gain can be calculated for any gain register value by using
the following equation:
Code Range
Gain Equation (dB)
0–1023
Gain
= (0.0353)(
Code
)
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 77 to 1023. The
Gain Accuracy Specifications also include a
PxGA
gain of approxi-
mately 3.3 dB, for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
V
127
255
383
511
639
767
895
1023
30
24
18
12
6
0
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference selected by the user in the clamp level
register. The clamp level is adjustable from 0 to 255 LSB, in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the postprocessing, the AD9845B optical black
clamping may be disabled using Bit D5 in the Operation Register
(see the Serial Interface Timing and Internal Register Descrip-
tion section). When the loop is disabled, the clamp level register
may still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least
20 pixels wide to minimize clamp noise. Shorter pulsewidths may
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