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參數資料
| 型號： | AD9862PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號前端（MxFE⑩）處理器 |
| 文件頁數： | 14/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9862PCB |
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REV. 0
–14–
AD9860/AD9862
Setting this bit high enables the decimation filters and decimates
the receive data by two.
REGISTER 8: Tx PWRDWN
BIT 5: Alt Timing Mode
The timing section in the data sheet describes two timing modes,
the
“
Normal Operation
”
and the
“
Alternate Operation
”
modes.
At power up, the default configuration is established from the
logic level of the Mode/TxBlank pin. If Mode/TxBlank is logic
low, the Normal Operation mode is the default; if the Mode/
TxBlank pin is held at a logic high, the Alternative Operation
mode is configured at power-up (the DLL is forced to multiply
by 4 at power-up by default in this mode). After power up, the
operation mode can be configured so that the Mode/TxBlank pin
can be used for other functions. To allow this, set this bit high.
BIT 4: TxOff Enable
By default, the Mode/TxBlank pin is not used for any transmit
synchronization. The Mode/TxBlank pin input can be used to
serve two functions, blanking the DAC outputs and slaving the
TxPGA gain control. When this bit is set high, a logic high on the
Mode/TxBlank pin forces the Tx digital block to stop clocking. In
this mode, the Tx outputs will be static, holding their last update
values. To slave the TxPGA gain control to the Mode/TxBlank
pin input, register Slave Enable (Register 17, Bit 1) needs to also
be programmed. See that register for more information.
BIT 3: Tx Digital (Power-Down)
By default this bit is low, enabling the transmit path digital to
operate as programmed through other registers. By setting this
bit high, the digital blocks are not clocked to reduce power con-
sumption. When enabled, the Tx outputs will be static, holding
their last update values.
BIT 0-2: Tx Analog (Power-Down)
Three options are available to reduce analog power consumption
for the Tx channels. The first two options disable the analog output
from Tx channel A or B independently, and the third option
disables the output of both channels and reduces the power
consumption of some of the additional analog support circuitry
for maximum power savings. With all three options, the DAC bias
current is not powered down so recovery times are fast (typically
a few clock cycles). The list below explains the different modes
and settings used to configure them.
Tx Analog
Power-Down
Bits Setting [2:0]
[1 0 0]
[0 1 0]
Power-Down Option
Power-Down Tx B Channel Analog Output
Power-Down Tx A Channel Analog Output
Power-Down Tx A and Tx B Analog Outputs [1 1 1]
REGISTER 10/11/12/13: DAC OFFSET A/B
DAC A/DAC B Offset
These 10-bit, twos complement registers control a dc current
offset that is combined with the Tx A or Tx B output signal. An
offset current of up to
±
12% I
OUTFS
(2.4 mA for a 20 mA full-
scale output) can be applied to either differential pin on each
channel. The offset current can be used to compensate for offsets
that are present in an external mixer stage, reducing LO leakage
at its output. Default setting is hex00, no offset current. The
offset current magnitude is set using the lower nine bits. Setting
the MSB high will add the offset current to the selected differen-
tial pin, while an MSB low setting will subtract the offset value.
DAC A/DAC B Offset Direction
This bit determines to which of the differential output pins for
the selected channel the offset current will be applied. Setting this
bit low will apply the offset to the negative differential pin. Setting
this bit high will apply the offset to the positive differential pin.
REGISTER 14/15: DAC GAIN A/B
BIT 6, 7: DAC A/DAC B Coarse Gain Control
These register bits will scale the full-scale output current (I
OUTFS
)
of either Tx channel independently. I
OUT
of the Tx channels is a
function of the R
SET
resistor, the TxPGA setting, and the Coarse
Gain Control setting.
MSB, LSB
Tx Channel Current Scaling
10 or 11
Does not scale output current
01
Scales output current by 1/2
00
Scales output current by 1/11
BIT 5–0: DAC A/DAC B Fine Gain
The DAC output curve can be adjusted fractionally through the
Gain Trim Control. Gain trim of up to
±
4% can be achieved on
each channel individually. The Gain Trim register bits are a twos
complement attention control word.
MSB, LSB
100000
Maximum positive gain adjustment
111111
Minimum positive gain adjustment
000000
No adjustment (default)
000001
Minimum negative gain adjustment
011111
Maximum negative gain adjustment
REGISTER 16: TxPGA GAIN
BIT 0–7: TxPGA Gain
This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) reg-
ister controls for the Tx programmable gain amplifier (TxPGA).
The TxPGA provides a 20 dB continuous gain range with 0.1 dB
steps (linear in dB) simultaneously to both Tx channels. By
default, this register setting is hex00.
MSB, LSB
000000
Minimum gain scaling
–
20 dB
111111
Maximum gain scaling 0 dB
REGISTER 17: Tx MISC
BIT 1: Slave Enable
The TxPGA Gain is controlled through register TxPGA Gain
setting and by default is updated immediately after the register
write. If this bit is set, the TxPGA Gain update is synchronized
with the rising edge of a signal applied to the Mode/TxBlank
pin. Setting TxOff enable in Register 8 is also required.
BIT 0: TxPGA Fast (Update Mode)
The TxPGA Fast bit controls the update speed of the TxPGA.
When Fast Update mode is enabled, the TxPGA provides fast gain
settling within a few clock cycles. Default setting for this bit
is low, which indicates Normal Update mode. Fast mode is
enabled when this bit is set high.
REGISTER 18: Tx IF (INTERFACE)
BIT 6: Tx Retime
The Tx path can use either of the clock outputs, CLKOUT1 or
CLKOUT2, to latch the Tx input data. Since CLKOUT1 and
CLKOUT2 have slight phase offsets, this provides some timing
flexibility with the interface. By default, this bit is high and the
Tx input latches use CLKOUT1. Setting this bit low will force
the Tx latches to use CLKOUT2.
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| AD9860PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9863 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front-End (MxFE⑩) Baseband Transceiver for Broadband Applications |
| AD9863-50EB | 制造商:Analog Devices 功能描述:12 BIT, 50 MSPS MXFE CONVERTER - Bulk |
| AD9863-50EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Mixed-Signal Front-End Baseband Transceiver For Broadband Applications 制造商:Analog Devices 功能描述:MIXED-SGNL FRONT-END (MXFE) BASEBAND TRNSCVR FOR BROADBAND A - Bulk |
| AD9863BCP-50 | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT, 50 MSPS MXFE DUAL CONVERTER - Bulk 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9863 |
| AD9863BCPRL-50 | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
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