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參數資料
| 型號： | AD9870EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數字化子系統 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 233K |
| 代理商： | AD9870EB |
–14–
)
REV. 0
5
FREQUENCY
–
MHz
0.01
A
–
–
5
–
15
–
25
–
35
–
45
–
55
–
65
0.1
1
10
–
75
–
85
–
95
f
CLK
/8
f
CLK
= 15MSPS
f
CLK
= 18MSPS
f
CLK
= 13MSPS
Figure 9b. Measured Normalized AAF Frequency Response
for AAR = 0
×
60 Setting with f
CLK
= 13, 15, and 18 MHz
5
FREQUENCY
–
MHz
0.1
A
–
–
5
–
15
–
25
–
35
–
45
–
55
–
65
1
10
100
AAR = 0
30
AAR = 0
60
AAR = 0
C0
Figure 9c. Measured AAF Frequency Response for Differ-
ent AAR Settings with f
CLK
= 18 MHz
Changing the AAR setting from the recommended value of 0
×
60
scales the frequency axis in an inverse way as shown in Figure
9c. For example, to scale the frequency response down by a
factor of 1.5 set the AAR register to 1.5 times 0
×
60 (i.e., 0
×
90).
This AAR setting will not cause an error flag to be set for
f
CLK
= 18 MHz since the 3.7 MHz cutoff is within the guaranteed
range. For f
CLK
= 18 MHz, this AAR setting would increase the
attenuation at the first alias by 10 dB, lower the –3 dB cutoff
from 5.6 MHz to 3.7 MHz, and reduce the mixer gain by 0.8 dB
due to the reduced mixer pole frequency
. However,
reducing
f
CLK
to 13 MHz while using the same AAR setting in many parts
may cause a deviation in the normalized frequency response
since the –3 dB cutoff of 2.7 MHz is well below the 3.5 MHz
lower limit. In general, –3 dB cutoff frequencies can be approxi-
mated by the following equation:
f
–
3
dB
=
(f
CLK
/3.2)
×
(0
×
60/
AAR
)
where
AAR
is the hexadecimal contents of the AAR register and
0
×
60 is its hexadecimal default setting.
Table VIII. SPI Registers Associated with AAF
Address
(Hex)
Bit
Breakdown Width
Default Value
Name
0x1C
0x1D
(7:0)
5
(4:0)
5
(4:0)
8
1
5
1
15
0x00
0
0x0
0
0x0
AAR
ERRN
CAPN
ERRP
CAPP
0x1E
VARIABLE GAIN AMPLIFIER OPERATION WITH
AUTOMATIC GAIN CONTROL
The AD9870 contains a variable gain amplifier (VGA) as well as
all of the necessary signal estimation and control circuitry to
implement automatic gain control (AGC) as shown in Figure
10. The AGC control circuitry provides a high degree of pro-
grammability to allow the user to optimize the AGC response as
well as the AD9870’s dynamic range for a given application.
The VGA is programmable over a 25 dB (typ) range and imple-
mented in the same circuitry as the AAF circuitry previously
discussed. Since its input is self-biasing and presents a high
impedance to the mixer output load, the differential output
signal appearing at the mixer output (MXOP, MXON) must be
ac coupled to the VGA input (IF2P, IF2N) with 0.1
μ
F ceramic
chip capacitors.
Note, an external 20 k
resistor in parallel with a
0.1
μ
F capacitor from VCM (Pin 13) to GNDA is required to ensure
common-mode compatibility between the ADC input and VGA output.
The purpose of the VGA is to extend the usable dynamic range
of the AD9870 by allowing the sigma-delta ADC to digitize low
level signals in the presence of larger unfiltered interferer signals
without saturation or “clipping” the ADC. The VGA can oper-
ate in either a user controlled variable gain control mode or
automatic gain control (AGC) mode. The VGA may also be
disabled using the VGA standby bit located in the STBY register.
Note, ideally the quiescent current of the VGA circuitry should
reduced from 6 mA to 0 mA when the standby is invoked. How-
ever, it has been found that the standby current increases to
1.3 mA a few seconds (temperature dependent) after placing
the VGA in standby. Hence, the user is recommended to write
to the STBY register periodically (0.1 kSPS) and toggle the
VGA bit (i.e., write 0 followed by 1) to ensure that the standby
current remains at approximately 0 mA.
VGA
DAC
ej(2 f
CLK
/8)t
VGA/
AAF
C
DAC
G
G
IF2P
IF2N
- ADC
f
CLK
DEC1
20
20
I
Q
A
BS
(I[N])+A
BS
(Q[N])
AGCR
REF LEVEL
AGC
CONTROL
ADC
CLIP POINT
OLW
1
(1
–
Z
–
1
)
f
CLK/20
Figure 10. Functional Block Diagram of VGA and AGC
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