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參數資料
| 型號： | AD9876-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 模擬前端 |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調制解調器混合信號前端 |
| 文件頁數： | 22/24頁 |
| 文件大小： | 666K |
| 代理商： | AD9876-EB |
REV. A
AD9876
–22–
Bit 2: Wideband Rx LPF
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the Rx path gain is limited
to 30 dB.
Bit 3: Fast ADC Sampling
Setting this bit increases the quiescent current in the SVGA
block. This may provide some performance improvement
when the ADC sampling frequency is greater than 50 MSPS
(in 6-Bit Mode).
Bit 4: Rx Digital HPF Bypass
Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.
Bit 5: Rx Path DC Offset Correction
Writing a 1 to this bit triggers an immediate receive path offset
correction and reads back zero after the completion of the offset
correction.
Bit 6: Rx LPF Tuning in Progress
This bit indicates when the receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 ms.
Writing to this bit has no effect.
Bit 7: Rx Port Negative Edge Sampling
Setting this bit high disables the automatic background receive
filter calibration. The AD9876 automatically calibrates the
receive filter on reset and every few (~2) seconds thereafter to
compensate for process and temperature variation, power sup-
ply, and long term drift. Programming a 1 to this bit disables
this function. Programming a 0 triggers an immediate first cali-
bration and enables the periodic update.
REGISTER 5—RECEIVE FILTER TUNING TARGET
This register sets the filter tuning target as a function of f
OSCIN
.
See Register 4 description.
REGISTER 6—Rx PATH GAIN ADJUST
The AD9876 uses a combination of a continuous time PGA
(CPGA) and a switched capacitor PGA (SPGA) for a gain range
of –6 dB to +36 dB with a resolution of 2 dB. The Rx path gain
can be programmed over the serial interface by writing to the
Rx Path Gain Adjust Register or directly using the GAIN and
MSB aligned Tx [5:1] Bits. The register default value is 0
×
00
for the lowest gain setting (–6 dB). The register always reads
back the actual gain setting irrespective of which of the two
programming modes were used.
Table V describes the gains and how they are achieved as a
function of the Rx Path adjust bits.
Bit 5: PGA Gain Set by Register
Setting this bit high will result in the Rx Path Gain being set by
writing to the PGA Gain Control Register. Default is zero which
selects writing the gain through the Tx [5:1] pins in conjunction
with the gain pin.
Table V. PGA Programming Map
Rx Path
Gain [4:0]
0
×
00
0
×
01
0
×
02
0
×
03
0
×
04
0
×
05
0
×
06
0
×
07
0
×
08
0
×
09
0
×
0A
0
×
0B
0
×
0C
0
×
0D
0
×
0E
0
×
0F
0
×
10
0
×
11
0
×
12
*
0
×
13
*
0
×
14
*
0
×
15
*
Rx Path
Gain
CPGA
Gain
SPGA
Gain
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30/30
30/32
30/34
30/36
–6
–6
–6
–6
–6
–6
0
0
0
6
6
6
12
12
12
18
18
18
18/24
18/24
18/24
18/24
0
2
4
6
8
10
6
8
10
6
8
10
6
8
10
6
8
10
12/6
12/8
12/10
12/12
*
When the Wideband Rx Filter Bit is set high, the Rx Path Gain is limited to
30 dB. The first of the two values in the chart refers to this mode. The second
number refers to the mode when the lower Rx LPF Cutoff Frequency is cho-
sen, or the Rx LPF Filter is bypassed.
REGISTER 7—TRANSMIT PATH SETTINGS
The AD9876 transmit path has a programmable interpolation
filter that proceeds the transmit DAC. The interpolation filter
can be programmed to operate in seven different modes. Also,
the digital interface can be programmed to operate in several
different modes. These modes are described below.
Bit 0: Transmit Port Demultiplexer Bypass
Setting Bit 0 high bypasses the input data demultiplexer. In this
mode, consecutive nibbles on the Tx [5:0] pins are treated as
individual words to be sent through the Tx path. This creates a
six bit data path. The state of Tx SYNC is ignored in this mode.
Bit 2: Transmit Port Least Significant Nibble First
Setting Bit 2 high reconfigures the AD9876 for a Transmit
Mode that expects least significant nibble before the most
significant nibble.
Bit 3: Power-Down Interpolator at
Tx QUIET
Pin Low
Setting Bit 3 high enables the
Tx QUIET
pin to shut off the
DAC output. If the bit is set to 1, then pulling the
Tx QUIET
pin low will power down the interpolator filters. In most appli-
cations, the interpolator filter will need to be flushed with 0s
before or after being powered down.
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相關代理商/技術參數 |
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| AD9877ABS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9877ABS-1 | 制造商:Analog Devices 功能描述: |
| AD9877ABSZ | 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9877BS | 制造商:Analog Devices 功能描述: |
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