
REV. A
AD9876
–4–
Test
Level
Parameter
Temp
Min
Typ
Max
Unit
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2
×
Interpolation
Tx Setup Time (t
SU
)
Tx Hold Time (t
HD
)
Rx PATH INTERFACE
Maximum Output Nibble Rate
Rx Data Valid Time (t
VT
)
Rx Data Hold Time (t
HT
)
SERIAL CONTROL BUS
Maximum SCLK Frequency (f
SCLK
)
Clock Pulsewidth High (t
PWH
)
Clock Pulsewidth Low (t
PWL
)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (t
DS
)
Data Hold Time (t
DH
)
Data Valid Time (t
DV
)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
II
II
II
128
3.0
0
MHz
ns
ns
Full
Full
Full
II
II
II
110
MHz
ns
ns
3.0
1.5
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
25
18
18
MHz
ns
ns
ms
ns
ns
ns
1
25
0
20
Full
Full
Full
Full
25
°
C
II
II
II
II
III
V
DRVDD
– 0.7
V
V
μ
A
μ
A
μ
F
0.4
12
12
3
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Digital Output Rise/Fall Time
Full
Full
Full
II
II
II
V
DRVDD
– 0.6
V
V
ns
0.4
2.5
1.5
POWER SUPPLY
All Blocks Powered Up
I
S_TOTAL
(Total Supply Current)
I
S_TOTAL
(
Tx QUIET
Pin Asserted)
Digital Supply Current (I
DRVDD
+ I
DVDD
)
Analog Supply Current (I
AVDD
)
Power Consumption of Functional Blocks:
Rx LPF
ADC and SPGA
Rx Reference
Interpolator
DAC
PLL-B
PLL-A
Voltage Regulator Controller
All Blocks Powered Down
Supply Current I
S
, f
OSCIN
= 32 MHz
Supply Current I
S
, f
OSCIN
Idle
Power Supply Rejection
Tx Path (
V
S
= 10%)
Rx Path (
V
S
= 10%)
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sine Wave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB
Full
25
°
C
25
°
C
25
°
C
I
III
III
III
262
172
77
185
288
mA
mA
mA
mA
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
III
III
III
110
55
2
33
18
8
24
1
mA
mA
mA
mA
mA
mA
mA
mA
Full
Full
II
II
19
10
22
12
mA
mA
25
°
C
25
°
C
III
III
62
54
dB
dB
25
°
C
25
°
C
III
III
–75
–70
dB
dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (V
FB
with SI2301 Connected)
Line Regulation (
V
FB%
/
V
DVDD%
×
100%)
Load Regulation (
V
FB
/
I
LOAD
)
Maximum Load Current (I
LOAD
)
Full
25
°
C
25
°
C
Full
I
III
III
II
1.25
1.30
100
60
1.35
V
%
m
mA
250
Specifications subject to change without notice.