- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9883ABST-110 (ANALOG DEVICES INC) 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays PDF資料下載
參數(shù)資料
| 型號： | AD9883ABST-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 229K |
| 代理商： | AD9883ABST-110 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. B
AD9883A
–15–
Table VI. Control Register Map
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
00H
RO
7:0
Chip Revision
An 8-bit register that represents the silicon revision level.
Revision 0 = 0000 0000.
01H
*
R/
W
7:0
01101001
PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Greater values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
02H
*
R/
W
7:4
1101
****
PLL Div LSB
Bits [7:4] of this word are written to the LSBs [3:0] of the
PLL divider word.
03H
R/
W
7:3
01
******
Bits [7:6] VCO Range. Selects VCO frequency range.
(See PLL description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
**
001
***
04H
R/
W
7:3
10000
***
Phase Adjust
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
05H
R/
W
7:0
10000000
Clamp
Placement
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
06H
R/
W
7:0
10000000
Clamp
Duration
Number of clock periods that the Clamp signal is actively clamping.
07H
R/
W
7:0
00100000
Hsync Output
Pulsewidth
Red Gain
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000
Controls ADC input range (contrast) of each respective channel.
Greater values give less contrast.
09H
0AH
R/W
R/W
7:0
7:0
10000000
10000000
Green Gain
Blue Gain
0BH
R/W
7:1
1000000
*
Red Offset
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
0CH
0DH
R/W
R/W
7:1
7:1
1000000
*
1000000
*
Green Offset
Blue Offset
0EH
R/
W
7:0
0
*******
Sync Control
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in register 0EH.)
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync,
Logic 1 = Logic Low Sync.)
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 3. If set to Logic 0, the active interface
is selected via Bit 6 in register 14H.
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note that the
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both
syncs are active. (Bits 1, 7 = Logic 1 in register 14H.)
Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.)
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 0. If set to Logic 0, the active interface
is selected via Bit 3 in register 14H.
Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output
Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.
Note that the indicated
Vsync will be used only if Bit 1 is set to Logic 1.
*
1
******
**
0
*****
***
0
****
****
0
***
*****
0
**
******
0
*
*******
0
2-Wire Serial Register Map
The AD9883A is initialized and controlled by a set of registers,
which determine the operating modes. An external controller is
employed to write and read the control registers through the
two-line serial interface port.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9883ABST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883KST-110 | 110 MSPS Analog Interface for Flat Panel Displays |
| AD9883 | 110 MSPS Analog Interface for Flat Panel Displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9883ABST-140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP |
| AD9883ABST-RL110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABST-RL140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABSTZ-110 | 功能描述:IC FLAT PANEL INTERFACE 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883ABSTZ-140 | 功能描述:IC INTERFACE FLAT 140MHZ 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。