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參數(shù)資料
| 型號(hào)： | AD9883ABST-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大小： | 229K |
| 代理商： | AD9883ABST-110 |
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REV. B
AD9883A
–19–
0E
5
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Hsync Output Polarity
Table XI. Hsync Output Polarity Settings
Setting
SYNC
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default setting for this register is 0.
4
Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
0E
Table XII. Active Hsync Override Settings
Override
Result
0
1
Autodetermines the Active Interface
Override, Bit 3 Determines the Active Interface
The default for this register is 0.
3
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
0E
Table XIII. Active HSYNC Select Settings
Select
Result
0
1
HSYNC Input
Sync-on-Green Input
The default for this register is 0.
2
Vsync Output Invert
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
0E
Table XIV. Vsync Output Invert Settings
Setting
Vsync Output
0
1
Invert
No Invert
The default setting for this register is 0.
1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
0E
Table XV. Active Vsync Override Settings
Override
Result
0
1
Autodetermine the Active Vsync
Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
0E
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
Table XVI. Active Vsync Select Settings
Select
Result
0
1
Vsync Input
Sync Separator Output
The default for this register is 0.
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
0F
Table XVII. Clamp Input Signal Source Settings
Clamp Function
Function
0
1
Internally Generated Clamp Signal
Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
0F
Table XVIII. Clamp Input Signal Polarity Settings
Clamp Function
Function
1
0
Active Low
Active High
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
The power-up default value is Clamp Polarity = 1.
5 Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
0F
Table XIX. Power-Down Settings
Select
Result
0
1
Coast Input Pin
Vsync (See above Text)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9883ABST-140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP |
| AD9883ABST-RL110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABST-RL140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABSTZ-110 | 功能描述:IC FLAT PANEL INTERFACE 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883ABSTZ-140 | 功能描述:IC INTERFACE FLAT 140MHZ 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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