- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9883ABST-110 (ANALOG DEVICES INC) 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9883ABST-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 229K |
| 代理商： | AD9883ABST-110 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. B
AD9883A
–21–
13
7–0 Post-Coast
This register allows the coast signal to be applied follow-
ing the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7 Hsync Detect
This bit is used to indicate when activity is detected on
the Hsync input pin (Pin 30). If Hsync is held high or
low, activity will not be detected.
14
Table XXVII. Hsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The sync processing block diagram shows where this
function is implemented.
6 AHS – Active Hsync
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1
in this register determine which source is used. If both
Hsync and SOG are detected, the user can determine which
has priority via Bit 3 in register 0EH. The user can override
this function via Bit 4 in register 0EH. If the override bit
is set to Logic 1, then this bit will be forced to whatever
the state of Bit 3 in register 0EH is set to.
14
Table XXVIII. Active Hsync Results
Bit 7
(Hsync
Detect)
Bit 1
(SOG
Detect)
Bit 4,
Reg 0EH
(Override)
AHS
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 0EH
1
0
Bit 3 in 0EH
Bit 3 in 0EH
AHS = 0 means use the Hsync pin input for Hsync.
AHS = 1 means use the SOG pin input for Hsync.
The override bit is in register 0EH, Bit 4.
5 Detected Hsync Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 12).
14
Table XXIX. Detected Hsync Input Polarity Status
Hsync Polarity Status
Result
0
1
Negative
Positive
14
4 Vsync Detect
This bit is used to indicate when activity is detected on
the Vsync input pin (Pin 31). If Vsync is held steady high
or low, activity will not be detected.
Table XXX. Vsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
3 AVS – Active Vsync
This bit indicates which Vsync source is being used: the
Vsync input or output from the sync separator. Bit 4 in this
register determines which is active. If both Vsync and
SOG are detected, the user can determine which has
priority via Bit 0 in register 0EH. The user can override this
function via Bit 1 in register 0EH. If the override bit is set
to Logic 1, this bit will be forced to whatever the state of Bit 0
in register 0EH is set.
14
Table XXXI. Active Vsync Results
AVS = 0 means Vsync input.
AVS = 1 means Sync separator.
The override bit is in register 0EH, Bit 1.
2
Detected Vsync Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync output. The detection circuit’s location is-
shown in the Sync Processing Block Diagram (Figure 12).
14
Table XXXII. Detected Vsync Output Polarity Status
Vsync Polarity Status
Result
0
1
Active Low
Active High
14
1
This bit is used to indicate when sync activity is detected
on the Sync-on-Green input pin (Pin 49).
Sync-on-Green Detect
Table XXXIII. Sync-on-Green Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
0
Detected Coast Polarity Status
This bit reports the status of the Coast input polarity
detection circuit. It can be used to determine the polarity
of the Coast input. The detection circuit’s location is shown
in the Sync Processing Block Diagram (Figure 12).
14
Bit 4, Reg 14H
(Vsync Detect)
Bit 1, Reg 0EH
(Override)
AVS
1
0
X
0
0
1
0
1
Bit 0 in 0EH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9883ABST-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883KST-110 | 110 MSPS Analog Interface for Flat Panel Displays |
| AD9883 | 110 MSPS Analog Interface for Flat Panel Displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9883ABST-140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP |
| AD9883ABST-RL110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABST-RL140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP T/R |
| AD9883ABSTZ-110 | 功能描述:IC FLAT PANEL INTERFACE 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883ABSTZ-140 | 功能描述:IC INTERFACE FLAT 140MHZ 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。