- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9913 (Analog Devices, Inc.) Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9913 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器 |
| 文件頁(yè)數(shù)： | 24/32頁(yè) |
| 文件大小： | 473K |
| 代理商： | AD9913 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
AD9913
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
The user supplies PCLK, CS, R/W, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
2.
CS, R/W, and the address lines must meet the setup and
hold times relative to the 1
st
PCLK rising edge.
3.
The user releases the bus to read.
4.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
5.
CS must meet the set up and hold times to the 3
rd
PCLK
rising edge.
Rev. 0 | Page 24 of 32
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
1.
The user supplies the PCLK, CS, R/W, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
2.
CS, R/W, and the address lines must meet the set up and
hold times relative to the 1
st
PCLK rising edge.
3.
Data lines must meet the set up and hold times relative to
the 2
nd
PCLK rising edge.
4.
CS must meet the set up and hold times relative to the 3
rd
PCK rising edge.
PCLK
READ OPERATION
ADDR0
DATA0
DATA1
ADDR1
CS
R/W
ADDR/DATA
0.3ns
t
CHD
t
CSU
t
DVLD
t
AHD
t
ASU
3ns
0.3ns
8ns
3ns
0
Figure 33. Parallel Port Read Timing
PCLK
WRITE OPERATION
ADDR/DATA
CS
R/W
DATA1
ADDR1
DATA0
ADDR0
0.3ns
t
CHD
0.3ns
t
DHD
3ns
t
DSU
3ns
t
ASU
0.3ns
t
AHD
3ns
t
CSU
0
Figure 34. Parallel Port Write Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9913BCPZ1 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ-REEL71 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9920A | 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9923A | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| AD9923ABBCZ | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9913/PCBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 Sub 50mW 250MSPS (+) 10-bit DDS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9913/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ | 功能描述:IC DDS 10BIT DAC 250MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9913BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ-REEL7 | 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。