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參數(shù)資料
| 型號： | AD9945KCPZRL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 12-Bit 40 MHz CCD Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 180K |
| 代理商： | AD9945KCPZRL7 |
REV. A
AD9945
–11–
CCD MODE TIMING
N
N+1
N+2
N+9
N+10
t
ID
t
ID
t
S1
t
OD
N–10
N–9
N–8
N–1
N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
t
S2
t
CP
Figure 8. CCD Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
Figure 9. Typical CCD Mode Line Clamp Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9945 | Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9945KCP | Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9945KCPRL | Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9945KCPRL7 | Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9945KCPZ2 | Complete 12-Bit 40 MHz CCD Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9945KCPZRL72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 40 MHz CCD Signal Processor |
| AD9948 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9948AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9948AKCPZRL | 制造商:Analog Devices 功能描述: |
| AD9948KCP | 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MSPS, 3V ANALOG FRONT END - Bulk 制造商:Analog Devices 功能描述: |
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