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參數(shù)資料
| 型號： | AD9953 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的14位，1.8V CMOS的直接數(shù)字頻率合成器 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大小： | 473K |
| 代理商： | AD9953 |
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PRELIMINARY TECHNICAL DATA
Segment Final Address value for profile 2 is reached. At this point, instead of stopping the
sequence, it repeats starting with profile 0.
AD9953
Programming AD9953 Features
Phase Offset Control
A 14-bit phase-offset (
θ
) may be added to the output of the Phase Accumulator by means of the
Control Registers. This feature provides the user with three different methods of phase control.
The first method is a static phase adjustment, where a fixed phase-offset is loaded into the
appropriate phase-offset register and left unchanged. The result is that the output signal is offset by
a constant angle relative to the nominal signal. This allows the user to phase align the DDS output
with some external signal, if necessary.
The second method of phase control is where the user regularly UPDATEs the phase-offset register
via the I/O Port. By properly modifying the phase-offset as a function of time, the user can
implement a phase modulated output signal. However, both the speed of the I/O Port and the
frequency of sysclk limit the rate at which phase modulation can be performed.
The third method of phase control involves the RAM and the profile input pins. The AD9953 can
be configured such that the RAM drives the phase adjust circuitry. The user can control the phase
offset via the RAM in an identical manner allowed for frequency sweeping. See the RAM Control
and the Sweep Modes of Operation sections for details.
Phase/Amplitude Dithering
The AD9953 DDS core includes optional phase and/or amplitude dithering controlled via the
CFR1<20:16> bits.
Phase dithering is the randomization of the state of the least significant bits of each phase word.
Phase dithering reduces spurious signal strength caused by phase truncation by spreading the
spurious energy over the entire spectrum. The downside to dithering is a rise in the noise floor.
Amplitude dithering is similar, except it affects the output signal routed to the DAC.
The AD9953 uses a 32-bit linear feedback shift register (LFSR), shown in Figure 7 below, to
generate the pseudo random binary sequence that is used for both phase and amplitude dither data.
The LFSR will generate, at the sync_clk rate, the pseudo random sequence only if dithering is
enabled. The enable signal is the 4-input OR of the dithering control bits (CFR1<20:16>).
REV. PrB 1/30/03
Page 30
Analog Devices, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9953ASV | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953PCB | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9954 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954YSV | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954YSV-REEL7 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9953/PCB | 制造商:Analog Devices 功能描述:400 MSPS, 14BIT DGTL SYNTHESIZER - Bulk |
| AD9953ASV | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:AD9953 400 MSPS DDS W/ 14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9953 TQFP48 |
| AD9953YSV-REEL7 | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP T/R |
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