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參數資料
| 型號： | AD9953ASV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數： | 36/42頁 |
| 文件大小： | 473K |
| 代理商： | AD9953ASV |
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PRELIMINARY TECHNICAL DATA
Synchronizing Multiple AD9953s
The AD9953 product allows easy synchronization of multiple AD9953s. There are three modes of
synchronization available to the user: an automatic synchronization mode; a software controlled
manual synchronization mode; and a hardware controlled manual synchronization mode. In all
cases, when a user wants to synchronize two or more devices, the following considerations must be
observed. First, all units must share a common clock source. Trace lengths and path impedance of
the clock tree must be designed to keep the phase delay of the different clock branches as closely
matched as possible. Second, the I/O update signal’s rising edge must be provided synchronously
to all devices in the system. Finally, regardless of the internal synchronization method used, the
DVDD_I/O supply should be set to 3.3V for all devices that are to be synchronized. AVDD and
DVDD should be left at 1.8V.
In automatic synchronization mode, one device is chosen as a master, the other device(s)
will be slaved to this master. When configured in this mode, all the slaves will automatically
synchronize their internal clocks to the sync_clk output signal of the master device. To enter
automatic synchronization mode, set the slave device’s automatic synchronization bit
(CFR1<23>=1). Connect the SYNC_IN input(s) to the master SYNC_CLK output. The slave
device will continuously update the phase relationship of its sync_clk until it is in phase with the
SYNC_IN input, which is the sync_clk of the master device. When attempting to synchronize
devices running at sysclk speeds beyond 250MSPS, the high-speed sync enhancement enable bit
should be set (CFR2<11>=1).
In software manual synchronization mode, the user forces the device to advance the
sync_clk rising edge one sysclk cycle (1/4 sync_clk period). To activate the manual
synchronization mode, set the slave device’s software manual synchronization bit (CFR1<22> =1).
The bit (CFR1<22>) will be immediately cleared. To advance the rising edge of the sync_clk
multiple times, this bit will need to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN input pin is configured such that
it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge
on the SYNC_IN pin. To put the device into hardware manual synchronization mode, set the
hardware manual synchronization bit (CFR2<10>=1). Unlike the software manual synchronization
bit, this bit does not self-clear. Once the hardware manual synchronization mode is enabled, all
rising edges detected on the SYNC_IN input will cause the device to advance the rising edge of the
sync_clk by one sysclk cycle until this enable bit is cleared (CFR2<10=0).
AD9953
Using a Single Crystal To Drive Multiple AD9953 Clock Inputs
The AD9953 crystal oscillator output signal is available on the CrystalOut pin, enabling one crystal
to drive multiple AD9953s. In order to drive multiple AD9953s with one crystal, the CrystalOut
pin of the AD9953 using the external crystal should be connected to the REFCLK input of the
other AD9953.
REV. PrB 1/30/03
Page 36
Analog Devices, Inc.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9953PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:AD9953 400 MSPS DDS W/ 14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9953 TQFP48 |
| AD9953YSV-REEL7 | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP T/R |
| AD9953YSVZ | 功能描述:IC DDS DAC 14BIT 400MSPS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9953YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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