- 您現在的位置：買賣IC網 > PDF目錄373975 > ADAU1702 (Analog Devices, Inc.) SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs PDF資料下載
參數資料
| 型號： | ADAU1702 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SigmaDSP的28 - 56位音頻處理器雙ADC和4個DAC |
| 文件頁數： | 24/52頁 |
| 文件大?。?/td> | 773K |
| 代理商： | ADAU1702 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
ADAU1702
I
2
C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1702 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1702 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in Figure 24.
Note that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1702 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1 (read).
This causes the ADAU1702 SDA to reverse and begin driving
Rev. 0 | Page 24 of 52
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1702.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1702 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths ranging from one to
five bytes. The ADAU1702 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
Chip address,
R/W = 0
AS
Subaddress high
AS
Subaddress low
AS
Data Byte 1
AS
Data Byte 2
…
AS
Data Byte N
P
Figure 22. Single-Word I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
Data-
Word 1,
Byte 1
AS
Data-
Word 1,
Byte 2
AS
Data-
Word 2,
Byte 1
AS
Data-
Word 2,
Byte 2
AS
…
P
Figure 23. Burst Mode I
2
C Write Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data
Byte 1
AM
Data
Byte 2
…
AM
Data
Byte N
P
Figure 24. Single-Word I
2
C Read Format
S
Chip address,
R/W = 0
AS
Subaddress
high
AS
Subaddress
low
AS
S
Chip address,
R/W = 1
AS
Data-
Word 1,
Byte 1
AM
Data-
Word 1,
Byte 2
AM
…
P
Figure 25. Burst Mode I
2
C Read Format
相關PDF資料 |
PDF描述 |
|---|---|
| ADAU1702JSTZ | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| ADAU1702JSTZ-RL | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| ADC912A | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| ADC912AFP | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| ADC912AFS | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADAU1702JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1702JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1761 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| ADAU1761BCPZ | 功能描述:IC SIGMADSP CODEC PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:SigmaDSP® 標準包裝:2,500 系列:- 類型:PCM 數據接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數量:1 / 1 三角積分調變:是 S/N 比，標準 ADC / DAC (db):- 動態(tài)范圍，標準 ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應商設備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| ADAU1761BCPZ | 制造商:Analog Devices 功能描述:IC, AUDIO CODEC, 24BIT, 96KHZ, LFCSP-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。