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參數(shù)資料
| 型號(hào)： | ADC912A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 中文描述： | 微處理器的CMOS兼容的12位A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 237K |
| 代理商： | ADC912A |
REV. B
–2–
ADC912A–SPECIFICATIONS
10 V; External f
CLK
= 1.25 MHz; –40 C to +85 C applies to ADC912A/F unless otherwise noted.)
(V
DD
= +5 V 5%, V
SS
= –11.4 V to –15.75 V, V
REFIN
= –5 V, Analog Input O V to
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
STATIC ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Full-Scale Tempco
1
INL
DNL
V
ZSE
G
FSE
TCG
FS
–1
–1
–5
–6
+1
+1
+5
+6
15
LSB
LSB
LSB
LSB
ppm/
°
C
V
DD
= +5 V, V
SS
= –12 V
V
DD
= +5 V, V
SS
= –12 V
5
ANALOG INPUT
Input Voltage Range
Input Current Range
V
IN
I
IN
0
0
10
3
V
mA
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Consumption
Power Supply Rejection Ratio
I
DD
I
SS
P
DISS
PSRR+
PSRR–
V
DD
= +5 V
2
V
SS
= –12 V
2
V
DD
= +5 V
2
, V
SS
= –12 V
2
V
DD
=
±
5%, A
IN
= 10 V
V
SS
=
±
5%, A
IN
= 10 V
5
3
70
1/2
1/2
7
5
95
4
4
mA
mA
mW
LSB
LSB
DIGITAL INPUTS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Digital Input Capacitance
V
INH
V
INL
I
IN
C
IN
CS
,
RD
, HBEN
CS
,
RD
, HBEN
CS
,
RD
, HBEN
Digital Inputs,
CS
,
RD
, HBEN, CLKIN
2.4
V
V
μ
A
pF
0.8
±
1
10
7
DIGITAL OUTPUTS
Logic Input High Voltage
Logic Input Low Voltage
Three-State Output Leakage
Digital Input Capacitance
V
OH
V
OL
I
OZ
C
OUT
I
SOURCE
= 0.2 mA
I
SINK
= 1.6 mA
D
11
–D
D
11
–D
0/8
4
V
V
μ
A
pF
0.4
10
15
8
DYNAMIC PERFORMANCE
Conversion Time
TC
f
CLK
= 1.25 MHz
3
Synchronous Clock
Asynchronous Clock
10.4
11.2
μ
s
μ
s
10.4
NOTES
1
Guaranteed by design.
2
Converter inactive;
CS
,
RD
= High, A
= 10 V.
3
See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25
°
C. See Typical Performance
Characteristics for additional information.
Specifications subject to change without notice.
3k
C
L
DGND
DBN
A. HIGH-Z TO V
OH
(
t
3
)
AND V
OL
TO V
OH
(
t
6
)
C
L
3k
DGND
DBN
5V
B. HIGH-Z TO V
OL
(
t
3
)
AND V
OH
TO V
OL
(
t
6
)
Figure 3. Load Circuits for Access Time
3k
10pF
DGND
DBN
A. V
OH
TO HIGH-Z
10pF
3k
DGND
DBN
5V
B. V
OL
TO HIGH-Z
Figure 4. Load Circuits for Output Float Delay
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