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參數資料
| 型號： | ADD8502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:25-35 |
| 中文描述： | 整合式LCD灰度發生器 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 1436K |
| 代理商： | ADD8502 |
REV. 0
ADD8502
–11–
OPERATION
Transfer Function
The transfer function for the ADD8502 is given in the following
equations:
1. Digital-to-analog transfer function for DAC A. An output can
be derived from Equation 1 as:
V
V
D
OUTA
DD
2
A
=
+
1
1024
(1)
2. Digital-to-analog transfer function for DAC B. An output can
be derived from Equation 2 as:
V
D
V
OUTB
B
DD
2
=
1024
(2)
Where
D
A
and
D
B
are decimal equivalents of the binary codes
that are loaded to the DAC Register from 0 to 1023.
3. Using any programmed tap point from the 512 resistor string,
the system output can be derived from Equation 3:
V
V
(
V
T
512
V
TX
OUTA
OUTB
X
OUTB
=
)
(3)
Where
T
X
is any tap point of the 512 resistor string. It is mask
programmable.
V
TX
is the voltage output at any output (VO, ... V4)
and will switch between two voltages depending on the mask
programmed tap points.
Example:
V
DD
= 5 V,
D
A
= 1,000,
D
B
= 100, and
T
X
= 500.
C1
C3
C2
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
DB15 (MSB)
CONTROL BITS
DATA BITS
DON’T
CARE
DB0 (LSB)
Figure 4. Input Register Contents
V
OUTA
= 4.941 V
V
OUTB
= 0.244 V
V
TX
= 4.831 V
Equations 1–3 will provide a theoretical calculation of the out-
puts. The actual will vary with load, process, and architecture.
See Specifications table.
SERIAL INTERFACE
The ADD8502 has a 3-wire serial interface (
CS-LD
, SCK, and
D
IN
). The writing sequence begins by bringing the
CS-LD
line
LOW. Data on the D
IN
line is clocked into the 16-bit shift regis-
ter on the rising edge of SCK. The serial clock frequency can be
as high as 10 MHz. When the last data bit is clocked in,
CS-LD
line needs to be brought HIGH to load the DAC regis-
ters and the operation mode is dependent upon the control bits.
Input Shift Register
The input shift register is 16 bits wide (see Figure 4). The first
four control bits (C3, C2, C1, and C0) are used to set the different
operating modes of the device. The next 10 bits are the data bits
and the last two bits are “Don’t Cares.” This composes a full word
that is transferred to the DAC register on the rising edge of
CS-LD
.
In a normal write sequence, the
CS-LD
line is kept LOW for at
least 16 rising edges of SCK and then it is brought HIGH to
update the DACs. However, if
CS-LD
is brought HIGH before
the 16
th
rising edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operation mode occurs.
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