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參數(shù)資料
| 型號： | ADD8502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:25-35 |
| 中文描述： | 整合式LCD灰度發(fā)生器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 1436K |
| 代理商： | ADD8502 |
REV. 0
–2–
ADD8502–SPECIFICATIONS
R
L
100
C
L
16nF
V
COM
Figure 1. Slew Rate Diagram
(@ V
DD
= 5.0 V, 40 C
≤
T
A
≤
85 C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SYSTEM ACCURACY
V
OUT
Error
Swing Error
1
Mean Error
2
Mean Error between Adjacent Channels
3
Mean Error between V0 and V4
4
3
1
3
3
3
20
17
21
21
25
mV
mV
mV
mV
mV
(V
Pn
– V
Nn
) – (V
Pi
– V
Ni
)
(V
Pn
+ V
Nn
)/2 – (V
Pi
+ V
Ni
)/2)
DAC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity
5
Offset Error
Gain Error
10
±
0.25
±
0.5
±
0.4
±
0.15
Bits
LSB
LSB
% of FSR
% of FSR
DNL
INL
OUTPUT CHARACTERISTICS
Output Current
Short Circuit Current
Output Leakage Current in High-Z Mode
Slew Rate
Settling Time to 1%
Slew Rate
5
Settling Time to 1%
5
Phase Margin
I
OUT
I
SC
I
LEAKAGE
SR
t
S
SR
t
S
φ
o
(V
DD
– 1 V)
Short to Ground
High-Z Mode
R
L
= 100 k
V0
to V4
Step Size
L
D
=100
Series 16 nF
V0
to V4
Step Size
25
60
0.01
1.25
8
0.7
8
67
mA
mA
μ
A
V/
μ
s
μ
s
V/
μ
s
μ
s
Degrees
1.0
12
12
V
COM
SWITCHES ACTIVE IMPEDANCE
COM to V
DD
COM to GND
COM to COM_M
COM to V4
Z
Z
Z
Z
See Table IV
25
25
25
25
50
50
50
50
I = 20 mA
MASK PROGRAMMABLE
RESISTOR CHAIN
Resistor Matching
R
MATCH
Any Two Segments between
512 Resistor String
1
%
POWER SUPPLY
Supply Voltage
Supply Current
Shutdown Supply Current
Sleep Supply Current
Shutdown Recovery Time
Sleep Recovery Time
V
DD
I
SY
I
SY-GLB
I
SY-GS1-3
4.5
190
5
270
0.2
175
23
10
5.5
400
1
210
30
15
V
μ
A
μ
A
μ
A
μ
s
μ
s
V
DD
= 5 V; No Load
Full Shutdown Mode
Mid 3 Buffers Shutdown
Global PD to 1%
V1–V3 Off to 1%
140
LOGIC SUPPLY
Logic Input Voltage Level
Logic Input Current
V
L
I
VL
2.3
3.3
0.01
5.5
1
V
μ
A
DIGITAL I/O
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
V
IH
V
IL
I
IN
C
IN
V
L
0.7
V
V
μ
A
pF
V
L
0.3
±
1
10
GND
≤
V
IN
≤
5.5 V
NOTES
1
Swing error is a comparison of measured V
OUT
step versus theoretical V
OUT
step. Theoretical values can be found on the Mask Tap Point Option sheet.
2
Mean error is measured V
OUT
mean versus theoretical V
OUT
mean (see Figure 3).
3
Mean errors between two adjacent channels versus theoretical (see Figure 3).
4
Mean errors between V0 and V4 versus theoretical (see Figure 3).
5
Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1).
Specifications subject to change without notice.
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