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參數(shù)資料
| 型號(hào)： | ADF4251BCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual Fractional-N/Integer-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24 |
| 封裝： | 4 X 4 MM, MO-200-VGGD2, LFCSP-24 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 387K |
| 代理商： | ADF4251BCP-REEL |
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REV. 0
–24–
ADF4251
For example, in a GSM1800 system, where 540 MHz IF fre-
quency output (IF
OUT
) is required, a 13 MHz reference frequency
input (REF
IN
) is available and a 200 kHz channel resolution
(F
RES
) is required on the IF output. The prescaler is set to 16/17.
IF REF
IN
doubler is disabled.
By Equation 5:
200
13
1 0
R
kHz
MHz
=
￥
if
R
= 65.
By Equation 6:
540
200
16
(
MHz
kHz
=
￥
￥
)
+
[
]
B
A
if
B
= 168 and
A
= 12.
Modulus
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (F
RES
) required at
the RF output. For example, a GSM system with 13 MHz
REF
IN
would set the modulus to 65. This means that the RF
output resolution (F
RES
) is the 200 kHz (13 MHz/65) necessary
for GSM.
Reference Doubler and Reference Divider
There is a reference doubler on-chip. This allows the input
reference signal to be doubled. This is useful for increasing the
PFD comparison frequency. Making the PFD frequency higher
improves the noise performance of the system. Doubling the
PFD frequency will usually result in an improvement in noise
performance of 3 dB. It is important to note that the PFD can-
not be operated above 30 MHz. This is due to a limitation in
the speed of the - circuit of the N divider.
12-Bit Programmable Modulus
Unlike most other fractional-N PLLs, the ADF4251 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configurations
for his or her application, when combined with the reference
doubler and the 4-bit R counter.
Take for example an application that requires 1.75 GHz RF and
200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This would result
in the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then
fed into the PFD. The modulus is now programmed to divide by
130. This also results in 200 kHz resolution. This would offer
superior phase noise performance over the previous setup.
The programmable modulus is also very useful for multistandard
applications. If a dual-mode phone requires PDC and GSM1800
standards, the programmable modulus is of huge benefit. PDC
requires 25 kHz channel step resolution, whereas GSM1800
requires 200 kHz channel step resolution. A 13 MHz reference
signal could be fed directly to the PFD. The modulus would be
programmed to 520 when in PDC mode (13 MHz /520 = 25 kHz).
The modulus would be reprogrammed to 65 for GSM1800
operation (13 MHz/65 = 200 kHz). It is important that the PFD
frequency remains constant (13 MHz). This allows the user to
design one loop filter that can be used in both setups without
running into stability issues. It is the ratio of the RF frequency
to the PFD frequency that affects the loop design. Keeping this
relationship constant and instead changing the modulus factor,
results in a stable filter.
Spurious Optimization and Fastlock
As mentioned in the Noise and Spur Setting section, the part can
be optimized for spurious performance. However, in fast-lock-
ing applications, the loop bandwidth needs to be wide.
Therefore, the filter does not provide much attenuation of the
spurious. The programmable charge pump can be used to get
around this issue. The filter is designed for a narrow loop band-
width so that steady-state spurious specifications are met. This is
designed using the lowest charge pump current setting. To
implement fastlock during a frequency jump, the charge pump
current is set to the maximum setting for the duration of the jump.
This has the effect of widening the loop bandwidth, which im-
proves lock time. When the PLL has locked to the new frequency,
the charge pump is again programmed to the lowest charge pump
current setting. This will narrow the loop bandwidth to its origi-
nal cutoff frequency to allow for better attenuation of the
spurious than the wide loop bandwidth.
Spurious Signals
—
Predicting Where They Will Appear
Just as in integer-N PLLs, spurs will appear at PFD frequency
offsets on either side of the carrier (and multiples of the PFD
frequency). In a fractional-N PLL, spurs will also appear at
frequencies equal to the RF
OUT
channel step resolution (F
RES
).
The ADF4251 uses a high order fractional interpolator engine.
This results in spurious signals also appearing at frequencies equal
to 1/2 of the channel step resolution. For example, examine the
GSM-1800 setup with a 26 MHz PFD and 200 kHz resolution.
Spurs will appear at ±26 MHz from the RF carrier (at an extremely
low level due to filtering). Also, there will be spurs at ±200 kHz from
the RF carrier. Due to the fractional interpolator architecture
used in the ADF4251, spurs will also appear at ±100 kHz from
the RF carrier. Harmonics of all spurs mentioned will also appear.
With lowest spur setting enabled, the spurs will be attenuated
into the noise floor.
Prescaler
The prescaler limits the INT value. With P = 4/5, N
MIN
= 31.
With P = 8/9, N
MIN
= 91.
The prescaler can also influence the phase noise performance.
If INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance.
Filter Design: ADIsimPLL
A filter design and analysis program is available to help users
implement their PLL design. Visit
www.analog.com/pll
for a
free download of the ADIsimPLL software. The software
designs, simulates, and analyzes the entire PLL frequency
domain and time domain response. Various passive and active
filter architectures are allowed.
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| ADF4251BCP-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Fractional-N/Integer-N Frequency Synthesizer |
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