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參數資料
| 型號： | ADF4251BCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual Fractional-N/Integer-N Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC24 |
| 封裝： | 4 X 4 MM, MO-200-VGGD2, LFCSP-24 |
| 文件頁數： | 5/28頁 |
| 文件大小： | 387K |
| 代理商： | ADF4251BCP-REEL |
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REV. 0
ADF4251
–5–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
CP
RF
CP
GND
1
RF
IN
A
RF
IN
B
A
GND
1
MUXOUT
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
RF Charge Pump Ground
Input to the RF Prescaler. This small signal input is normally taken from the VCO.
Complementary Input to the RF Prescaler
Analog Ground for the RF Synthesizer
This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-
quency to be accessed externally.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance of
100 k
W
. This input can be driven from a TTL or CMOS crystal oscillator.
Chip Enable. A Logic Low on this bit powers down the device and puts the charge pump outputs into three-state.
A Logic High on this pin powers up the device, depending on the status of the software power-down bits.
Digital Ground for the Fractional Interpolator
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
seven latches, the latch being selected using the control bits.
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship
between
I
CP
and
R
SET
is:
=
1 6875
REF
IN
CE
D
GND
CLK
DATA
LE
R
SET
Therefore, with
R
SET
= 2.7 k
W
,
I
CP MIN
= 0.625 mA.
Ground for the IF Synthesizer
Complementary Input to the IF Prescaler
Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.
Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. DV
DD
must have the same voltage as V
DD
1, V
DD
2, and V
DD
3.
IF Charge Pump Ground
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to V
DD
2.
Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as
possible to this pin. V
DD
2 has a value 3 V ± 10%. V
DD
2 must have the same voltage as V
DD
1, V
DD
3, and DV
DD
.
Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. V
DD
3 has a value 3 V ± 10%. V
DD
3 must have the same voltage as V
DD
1, V
DD
2, and DV
DD
.
Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. V
DD
1 has a value 3 V ± 10%. V
DD
1 must have the same voltage as V
DD
2, V
DD
3, and DV
DD
.
RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to V
DD
1.
I
R
CP MIN
SET
.
A
GND
2
IF
IN
B
IF
IN
A
DV
DD
CP
GND
2
CP
IF
V
P
2
V
DD
2
V
DD
3
V
DD
1
V
P
1
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