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| 型號(hào)： | ADM1041A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | 二次側(cè)電流控制器共享和管家 |
| 文件頁(yè)數(shù)： | 33/56頁(yè) |
| 文件大小： | 991K |
| 代理商： | ADM1041A |
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ADM1041A
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1041A contains volatile registers (RAM) and
nonvolatile EEPROM. RAM occupies the address locations
from 00h to 7Fh, while EEPROM occupies the address locations
from 8000h to 813Fh.
Rev. 0 | Page 33 of 56
The SMBus specification defines several protocols for different
types of read and write operations. The protocols used in the
ADM1041A are described and illustrated in this section. The
following abbreviations are used in the diagrams:
S
Start
P
Stop
R
Read
W
Write
A
Acknowledge
A
No Acknowledge
The ADM1041A uses the following SMBus write protocols.
SMBus Erase EEPROM Page Operations
EEPROM memory can be written to only if it is effectively
unprogrammed. Before writing to one or more locations that
are already programmed, the page containing those locations
must be erased. EEPROM ERASE is performed by sending a
page erase command byte (A2h) followed by the page location
of the item to be erased. (There is no need to set an erase bit in
an EEPROM control/status register.)
The EEPROM consists of 16 pages of 32 bytes each; the register
default EEPROM consists of 1 page of 32 bytes starting at
8100h.
Table 7. EEPROM Page Layout
Page No.
EEPROM Location
1
8000h to 801Fh
2
8020h to 803Fh
3
8040h to 805Fh
4
8060h to 807Fh
5
8080h to 809Fh
6
80A0h to 80BFh
7
80C0h to 80DFh
8
80E0h to 80FFh
9
8100h to 811Fh
10
8120h to 813Fh
11
8140h to 815Fh
12
8160h to 817Fh
13
8180h to 819Fh
14
81A0h to 81BFh
15
81C0h to 81DFh
16
81E0h to 81FFh
Description
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Configuration Boot Registers
ADI Registers
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
ADI Registers
The EEPROM page address consists of the EEPROM address
high byte, 80h for FRU or 81h for register default, and the three
MSBs of the low byte. The lower five bits of the EEPROM
address of the low byte are ignored during an erase operation.
ASLAVE
S
EEPROM
HIGH BYTE
(80h OR 81h)
ARBITRARY
DATA
EEPROM
LOW BYTE
(00h TO FFh)
COMMAND A2h
(PAGE ERASE)
W A
A P
A
A
7
A
10
8
11 12
9
2
1
6
4
3
5
0
Figure 28. EEPROM Page Erase Operation
Page erasure takes approximately 20 ms. If the EEPROM is
accessed before erasure is complete, the SMBus responds with
No Acknowledge.
Figure 29 shows the peak IDD supply current during an
EEPROM page erase operation. Decoupling capacitors of 10 μF
and 100 nF are recommended on V
DD
.
0
Figure 29. EEPROM Page Erase Peak I
DD
Current
SMBus Write Operations
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code.
The slave asserts ACK on SDA.
The master asserts a stop condition on SDA and the
transaction ends.
In the ADM1041A, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address or block read or write starting at that address.
This is illustrated in Figure 30.
3.
4.
5.
6.
SLAVE
ADDRESS
S
RAM
ADDRESS
(00h TO 7Fh)
W A
A P
4
5
6
2
1
3
0
Figure 30. Setting a RAM Address for Subsequent Read
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