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參數資料
| 型號： | ADM1041A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | 二次側電流控制器共享和管家 |
| 文件頁數： | 34/56頁 |
| 文件大?。?/td> | 991K |
| 代理商： | ADM1041A |
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ADM1041A
If it is required to read data from the RAM immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read, block read, or block write operation without
asserting an intermediate stop condition.
Write Byte/Word
In this operation, the master device sends a command byte and
one or two data bytes to the slave device, as follows:
Rev. 0 | Page 34 of 56
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code.
The slave asserts ACK on SDA.
The master sends a data byte.
The slave asserts ACK on SDA.
The master sends a data byte (or asserts stop at this point).
The slave asserts ACK on SDA.
10.
The master asserts a stop condition on SDA to end the
transaction.
3.
4.
5.
6.
7.
8.
9.
In the ADM1041A, the write byte/word protocol is used for
the following three purposes. The ADM1041A knows how to
respond by the value of the command byte.
Write a single byte of data to RAM. Here, the command
byte is the RAM address from 00h to 7Fh and the (only)
data byte is the actual data, as shown in Figure 31.
SLAVE
ADDRESS
S
DATA
W A
A P
A
6
7
8
5
2
1
3
0
RAM
ADDRESS
(00h TO 7Fh)
4
Figure 31. Single-Byte Write to RAM
Set up a 2-byte EEPROM address for a subsequent read or
block read. In this case, the command byte is the high byte
of the EEPROM address (80h). The (only) data byte is the
low byte of the EEPROM address, as shown in Figure 32.
SLAVE
ADDRESS
S
EEPROM
ADDRESS
HIGH BYTE
(80h OR 81h)
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
W
A P
A
A
6
7
8
5
2
1
4
3
0
Figure 32. Setting an EEPROM Address
If it is required to read data from the EEPROM immedi-
ately after setting up the address, the master can assert a
repeat start condition immediately after the final ACK and
carry out a single-byte read or a block read without
asserting an intermediate stop condition.
Write a single byte of data to EEPROM. In this case, the
command byte is the high byte of the EEPROM address,
80h or 81h. The first data byte is the low byte of the
EEPROM address and the second data byte is the actual
data. Bit 1 of EEPROM Register 3 must be set. This is
illustrated in Figure 33.
SLAVE
ADDRESS
S
EEPROM
ADDRESS
HIGH BYTE
(80h OR 81h)
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
W A
A P
A
5
A
6
9 10
7
2
1
4
3
0
DATA
8
Figure 33. Single-Byte Write to EEPROM
If it is required to read data from the ADM1041A immediately
after setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read, block read, or block write operation without
asserting an intermediate stop condition.
Block Write
In this operation, the master device writes a block of data to a
slave device. Programming an EEPROM byte takes
approximately 350 μs, which limits the SMBus clock for
repeated or block write operations. The start address for a block
write must have been set previously. In the case of the
ADM1041A, this is done by a send byte operation to set a RAM
address or by a write byte/ word operation to set an EEPROM
address.
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1041A command
code for a block read is A0h (10100000).
The slave asserts ACK on SDA.
The master sends a data byte that tells the slave device how
many data bytes are to be sent. The SMBus specification
allows a maximum of 32 data bytes to be sent in a block
write.
The slave asserts ACK on SDA.
The master sends N data bytes.
The slave asserts ACK on SDA after each data byte.
10.
The master asserts a stop condition on SDA to end the
transaction.
3.
4.
5.
6.
7.
8.
9.
SLAVE
ADDRESS
S
BYTE
COUNT
DATA 2
DATA 1
COMMAND A0h
(BLOCK WRITE)
W A
A P
A
A
7
A
DATA N
8
10
9
2
1
6
4
3
5
A
0
Figure 34. Block Write to EEPROM or RAM
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相關代理商/技術參數 |
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| ADM1041AARQZ | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監視器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041AARQZ-REEL | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監視器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041AARQZ-REEL7 | 功能描述:IC SECONDARY SIDE CTRLR 24QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監視器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADM1041A-EVALZ | 功能描述:BOARD EVAL FOR ADM1041A RoHS:是 類別:編程器，開發系統 >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 標準包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩壓器拓撲結構:降壓 頻率 - 開關:250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
| ADM1041ARQ | 功能描述:IC PWR SUPP MON/LOAD SHAR 24QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監視器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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