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參數資料
| 型號： | ADM708RAN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 129K |
| 代理商： | ADM708RAN |
REV. A
–4–
ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONS
Pin No.
ADM706
Pin No.
ADM708
Mnemonic
Function
MR
1
1
Manual Reset Input. When taken below 0.6 V a RESET is generated.
MR
can be
driven from TTL, CMOS logic or from a manual reset switch as it is internally
debounced. An internal 70
μ
A pull-up current holds the input high when floating.
Power Supply Input.
0 V. Ground reference for all signals.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.
Power Fail Output.
PFO
is the output from the Power Fail Comparator. It goes
low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output
WDO
goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.
No Connect.
Logic Output.
RESET
goes low for 200 ms when triggered. It can be triggered
either by V
CC
being below the reset threshold or by a low signal on the manual
reset (
MR
) input.
RESET
will remain low whenever V
CC
is below the reset
threshold. It remains low for 200 ms after V
CC
goes above the reset threshold or
MR
goes from low to high. A watchdog timeout will not trigger
RESET
unless
WDO
is connected to
MR
.
Logic Output. RESET is an active high output suitable for systems which use
active high RESET logic. It is the inverse of
RESET
.
Logic Output. The Watchdog Output,
WDO
, goes low if the internal watchdog
timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared.
WDO
also goes low during low line conditions.
Whenever V
CC
is below the reset threshold,
WDO
remains low. As soon as V
CC
goes above the reset threshold,
WDO
goes high immediately.
V
CC
GND
PFI
2
3
4
2
3
4
PFO
5
5
WDI
6
N/A
NC
RESET
N/A
7 (R/S/T Only)
6
7
RESET
7 (P Only)
8
WDO
8
N/A
PIN CONFIGURATIONS
MR
V
CC
GND
PFI
WDO
RESET
WDI
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM706
P
MR
V
CC
GND
PFI
NC = NO CONNECT
RESET
RESET
NC
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM708
R/S/T
MR
V
CC
GND
PFI
WDO
RESET
WDI
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM706
R/S/T
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