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參數(shù)資料
| 型號： | ADM708RAN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大小： | 129K |
| 代理商： | ADM708RAN |
REV. A
–8–
ADM706P/R/S/T, ADM708R/S/T
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, then WDO goes
low and a nonmaskable interrupt is generated. This interrupt
routine may be used to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, then the
WDO
output should be connected to the
input as shown in Figure 16.
ADM706
RESET
GND
I/O LINE
m
P
MR
PFI
WDI
WDO
RESET
Figure 16.
RESET
from WDO
Monitoring Additional Supply Levels
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors
R1 and R2 are selected such that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The
PFO
output
may be connected to the
MR
input so that a RESET is gener-
ated when the supply drops out of tolerance. In this case if
either supply drops out of tolerance, a RESET will be generated.
ADM706
PFI
RESET
GND
m
P
MR
WDI
PFO
RESET
V
CC
R1
R2
V
X
+3V/+3.3V
Figure 17. Monitoring 3 V/3.3 V and an Additional
Supply, V
X
m
Ps with Bidirectional
RESET
In order to prevent contention for microprocessors with a bidi-
rectional reset line, a current limiting resistor should be inserted
between the ADM70x
RESET
output pin and the
μ
P reset pin.
This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 k
. If the re-
set output is required for other uses, then it should be buffered
as shown in Figure 18.
ADM70x
RESET
GND
m
P
RESET
GND
BUFFERED
RESET
+3V/+3.3V
V
CC
Figure 18. Bidirectional I-O RESET
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
8-Lead Plastic DIP
(N-8)
P
C
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
1
4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
8
0
8
0.0196 (0.50)
0.0099 (0.25)
3
45
8
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
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