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參數資料
| 型號： | ADMC330BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 0-BIT, 20 MHz, OTHER DSP, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數： | 13/20頁 |
| 文件大小： | 163K |
| 代理商： | ADMC330BST |
ADMC330
–13–
REV. 0
Serial Ports
T he ADMC330 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
Following is a brief list of the capabilities of the ADMC330
SPORT s. Refer to the
ADSP-2100 Family User’s Manual
for
further details.
SPORT s are bidirectional and have a separate, double-buff-
ered transmit and receive section.
SPORT s can use an external serial clock or generate their
own serial clock internally.
SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and
μ
-law companding according
to CCIT T recommendation G.711.
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
SPORT 0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bit stream.
SPORT 1 can be configured to have two external interrupts
(
IRQ0
and
IRQ1
) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this
configuration.
SPORT 1 has two multiplexed data receive pins DR1A and
DR1B. DR1A is automatically selected at boot up and is the
default input for the serial ROM. For UART communication
DR1B is selected.
A full description of the SPORT timing parameters is given in
Figure 14.
Interrupts
T he interrupt controller allows the processor core to respond to
nine possible interrupts with the minimum of overhead. T he
ADMC330 supports eight internal interrupts from the timer,
the two serial ports, the software interrupts, and the software
forced power-down interrupt. T he ninth interrupt,
IRQ2
on the
2171 core, is actually wired internally to the ADMC330 periph-
eral interrupt sources. T his peripheral interrupt is generated on
a PWM trip, PWMSYNC (once each PWM cycle), or from any
of the eight PIO ports. T he PWMSYNC interrupt is triggered
by a low to high transition on the PWMSYNC pulse.
T he
PWMTRIP
interrupt is triggered on a high-to-low transi-
tion on the
PWMTRIP
pin. A PIO interrupt is detected on any
change of state (high-to-low or low-to-high) on the PIO line.
When a peripheral interrupt is detected, a flag bit is set in the
IRQFLAG register for PWMSYNC and
PWMTRIP
or in the
PIOFLAG register for a PIO interrupt, and the
IRQ2
line is
pulled low. T he
IRQ2
line is held low until all pending periph-
eral interrupts are acknowledged. Execution then begins at the
IRQ2
(or peripheral) interrupt vector location (0x004). Soft-
ware at this location further determines if the source of the
interrupt was a PWM trip, PWYMSYNC, or PIO, by reading
the IRQFLAG register, and vectors to the appropriate interrupt
vector location. If more than one interrupt occurs simultaneously,
the higher priority interrupt service routine is executed. T he
software at location 0x004 is provided in a default interrupt
vector table that is created by the on-chip boot ROM code.
T herefore, a user need only put the interrupt service routine
for the given interrupt at the interrupt vector location shown in
T able IV. Reading the IRQFLAG register clears the
PWMTRIP
and PWMSYNC bits and acknowledges the interrupt, thus
allowing further interrupts when the interrupt service routine
exits. When the IRQFLAG register is read, it is saved in a data
memory variable so the user interrupt service routines can check
to see if there were simultaneous
PWMTRIP
and PWMSYNC
interrupts.
A user’s PIO interrupt service routine must read the PIOFLAG
register to determine which PIO port is the source of the inter-
rupt. Reading the PIOFL AG register clears all bits in the
register and acknowledges the interrupt, thus allowing further
interrupts when the interrupt service routine exits.
All interrupts are internally prioritized and individually maskable
(except for power-down). T he interrupt vector locations and
priorities for all interrupts are listed in T able IV. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK ;
the higher priority unmasked interrupt is then selected. T he
software forced power-down interrupt is nonmaskable. T he
ADMC330 masks all interrupts for one instruction cycle follow-
ing the execution of an instruction that modifies the IMASK
register. T his does not affect autobuffering.
T able IV. Interrupt Priority and Interrupt Vector Addresses
Interrupt
Vector Location (Hex)
Source of Interrupt
Reset
PWMTRIP
and Power-Down*
PWMSYNC*
PIO*
SPORT 0 T ransmit
SPORT 0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT 1 T ransmit or
IRQ1
SPORT 1 Receive or
IRQ0
T imer
0x0000 (Reserved)
0x002C (Highest Priority)
0x000C
0x0008
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028 (Lowest Priority)
*Peripheral interrupt (
IRQ2
) starts execution at 0x004, software further vector
to 0x002C, 0x000C or 0x0008 as appropriate.
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