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參數資料
| 型號： | ADMC330BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Single Chip DSP Motor Controller |
| 中文描述： | 0-BIT, 20 MHz, OTHER DSP, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 163K |
| 代理商： | ADMC330BST |
ADMC330
–14–
REV. 0
T he interrupt control register, ICNT L, allows the external inter-
rupts to be either edge- or level-sensitive. Since the
IRQ2
line is
a combination of all peripheral interrupt sources, they will all be
set to edge- or level-sensitive. Level-sensitive is recommended
when using both PIO and PWM interrupts together. When
simultaneous PIO and PWM interrupts occur, the
IRQ2
line is
brought low and held low until both the PIO and PWM inter-
rupts are acknowledged. If interrupts are set to edge-sensitive
only, one
IRQ2
interrupt will occur for simultaneous interrupts
and it is incumbent on the interrupt service routine to check for
simultaneous interrupts. If, however, interrupts are set to level-
sensitive, all simultaneous interrupts are detected because
IRQ2
is held low until all interrupts are acknowledged.
T he ICNT L register also allows interrupts to be sequentially
processed or nested with higher priority interrupts taking prece-
dence. Since the peripheral interrupts are all on the same level
(
IRQ2
), they can only be nested by manually unmasking them
with the IMASK register from inside the interrupt service routine.
T he IFC register is a write-only register, which is used to force
and clear interrupts from software.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. T he stacks are 12
levels deep to allow interrupt nesting. A set of shadow registers
are provided for single context switching.
Power-Down
T he ADMC330 can be put in a lower power state from software
control by setting the PDFORCE bit in the SPORT 1 Autobuffer/
Power-Down register. T his causes a power-down interrupt;
execution then continues at the power-down interrupt vector
location 0x002C. T he power-down interrupt vector location is
shared with the
PWMTRIP
interrupt, thus if a different inter-
rupt service routine is required, the vector must be changed
prior to setting the PDFORCE bit. T he power-down interrupt
service routine must perform a peripheral reset prior to entering
power-down to shut down the PWM signals to the motor. T he
interrupt service routine can then perform any housekeeping
operations prior to executing an IDLE instruction, after which
the ADMC330 is in power-down mode. T he only way out of
power-down is to perform a hardware reset of the ADMC330.
Clock Signals
T he ADMC330 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLK IN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
If an external clock is used, it should be a T T L -compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLK IN input. When an external clock
is used, the X T AL input
must
be left unconnected.
T he ADMC330 uses an input clock with a frequency equal to
half the instruction rate; a 10 MHz input clock yields a 50 ns
processor cycle (which is equivalent to 20 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLK OUT signal when enabled.
Because the ADMC330 includes an on-chip oscillator circuit,
an external crystal may be used. T he crystal should be con-
nected across the CLK IN and X T AL pins, with two capacitors
connected as shown in Figure 10. A parallel-resonant, funda-
mental frequency, microprocessor-grade crystal should be used.
10M
V
CLKIN
XTAL
Figure 10. External Crystal Connections
A clock output (CLK OUT ) signal is generated by the processor
at the processor’s cycle rate.
Reset
T he
RESET
signal initiates a master reset of the ADMC330.
T he
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLK IN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low.
T he
RESET
input contains some hysteresis; however, if you
use an RC circuit to generate your
RESET
signal, the use of an
external Schmitt trigger is recommended.
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When
RESET
is released, the DSP starts running from
the internal ROM and the boot loading sequence is performed.
If an SROM (serial ROM) or Serial EEPROM is connected to
SPORT 1 with valid program data, this code is then loaded and
execution starts. If a valid device is not detected, then the pro-
gram defaults to debug mode with SPORT 1 configured as a
UART running at 9600 baud.
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