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參數資料
| 型號： | ADMC401-PB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 單芯片，基于DSP的高性能電機控制器 |
| 文件頁數： | 2/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401-PB |
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RECOMMENDED OPERATING CONDITIONS
B Grade
Parameter
Min
Max
Unit
V
DD
AV
DD
T
AMB
ELECTRICAL CHARACTERISTICS
Digital Supply Voltage
Analog Supply Voltage
Ambient Operating Temperature
4.75
4.75
–40
5.25
5.25
+85
V
V
°
C
Parameter
Test Conditions
Min
Max
Unit
V
IH
V
IL
V
OH
HI-Level Input Voltage
1, 2, 3
LO-Level Input Voltage
1, 2, 3
HI-Level Output Voltage
1, 3, 4, 5, 6
@ V
DD
= max
@ V
DD
= min
@ V
DD
= min, I
OH
= –1.0 mA
@ V
DD
= min, I
OH
= –0.1 mA
@ V
DD
= min, I
OL
= 2.0 mA
@ V
DD
= min, I
OH
= –10.0 mA
@ V
DD
= min, I
OL
= 10.0 mA
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max
@ V
DD
= max
@ AV
DD
= max
V
IN
= 2.5 V, f
IN
= 1 MHz,
T
AMB
= +25
°
C
V
IN
= 2.5 V, f
IN
= 1 MHz,
T
AMB
= +25
°
C
2.0
V
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
pF
0.8
2.4
V
DD
– 0.3
V
OL
V
OH
V
OL
I
IH
I
IH
I
IH
I
IL
I
IL
I
IL
I
OZH
I
OZL
I
DD
I
DD
I
DD
C
I
LO-Level Output Voltage
1, 3, 4, 5, 6
HI-Level Output Voltage
5
LO-Level Output Voltage
5
HI-Level Input Current
7
HI-Level Input Current
8
HI-Level Input Current
9
LO-Level Input Current
7
LO-Level Input Current
8
LO-Level Input Current
9
HI-Level Three-State Leakage Current
10
LO-Level Three-State Leakage Current
10
Digital Supply Current (Idle)
11
Digital Supply Current (Dynamic)
12
Analog Supply Current
Input Pin Capacitance
13
0.4
2.4
1.2
10
100
10
10
10
100
10
10
40
110
60
8
C
O
Output Pin Capacitance
13, 14
8
pF
NOTES
Bidirectional pins: D0–D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0–PIO11.
2
Input only pins:
PWMTRIP
, PWMPOL,
PWMSR
,
RESET
, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE,
BR
and
PWD
.
3
Programmable I/O Pins (PIO0–PIO11).
4
Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1,
BG
,
BGH
,
PMS
,
DMS
,
BMS
,
RD
,
WR
, PWDACK and A0–A13.
5
Output pins: AH, AL, BH, BL, CH and CL.
6
Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to V
DD
–0.3 V and GND+0.3 V assuming no dc loads.
7
Input only pins
RESET
, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE,
BR
and
PWD
.
8
Input pins with internal pull-down PIO0–PIO11 and
PWMTRIP
.
9
Input pins with internal pull-up, PWMPOL and
PWMSR
.
10
Three-statable pins: A0–A13, D0–D23,
PMS
,
DMS
,
BMS
,
RD
,
WR
, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
11
Idle refers execution of the IDLE instruction. Deasserted pins are driven to V
DD
or GND. Current reflects device operation with CLKOUT disabled.
12
Current reflects device operating with no output loads.
13
Guaranteed but not tested.
14
Output Pin Capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
(V
DD
= AV
DD
= 5 V 5%, GND = AGND = 0 V, T
AMB
= –40 C to +85 C,
CLKIN = 13 MHz, unless otherwise noted)
REV. B
–2–
ADMC401–SPECIFICATIONS
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