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參數資料
| 型號： | ADN2812ACP-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁數： | 23/28頁 |
| 文件大小： | 478K |
| 代理商： | ADN2812ACP-RL |
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ADN2812
Rev. 0 | Page 23 of 28
0
50
50
PIN
V
REF
NIN
C
IN
C
OUT
C
OUT
V1
C
IN
V1b
V2
V2b
TIA
LIMAMP
CDR
+
–
VCC
DATAOUTP
DATAOUTN
1
V1
V1b
V2
V2b
V
DIFF
2
3
4
VREF
VTH
ADN2812
V
= V2–V2b
VTH = ADN2812 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2812. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 27. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2812 can also be dc-coupled. This might
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2812 are dc-coupled, care must be taken not
to violate the input range and common-mode level require-
ments of the ADN2812 (see Figure 28 through Figure 30). If dc
coupling is required, and the output levels of the TIA do not
adhere to the levels shown in Figure 29, then level shifting
and/or an attenuator must be between the TIA outputs and the
ADN2812 inputs.
0
50
0.1
μ
F
50
3k
NIN
PIN
ADN2812
2.5V
VREF
50
50
TIA
VCC
Figure 28. DC-Coupled Application
0
PIN
I
V
PP
= PIN – NIN = 2
×
V
SE
= 10mV AT SENSITIVITY
V
SE
= 5mV MIN
V
= 2.3V MIN
(DC-COUPLED)
NIN
Figure 29. Minimum Allowed DC-Coupled Input Levels
0
PIN
I
V
PP
= PIN – NIN = 2
×
V
SE
= 2.0V MAX
V
SE
= 1.0V MAX
V
= 2.3V
(DC-COUPLED)
NIN
Figure 30. Maximum Allowed DC-Coupled Input Levels
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