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| 型號(hào)： | ADN2819ACPZ-CML1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時(shí)鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器 |
| 文件頁(yè)數(shù)： | 13/24頁(yè) |
| 文件大小： | 570K |
| 代理商： | ADN2819ACPZ-CML1 |
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ADN2819
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed-loop bandwidth
of the delay-locked loop, which is roughly 5 MHz for OC-12,
OC-48, and GbE data rates, and 600 kHz for OC-3 data rates.
Rev. B | Page 13 of 24
JITTER PEAKING
IN ORDINARY PLL
ADN2819
Z(s)
X(s)
f
(kHz)
JITTER
GAIN
(dB)
o
n psh
d psh
c
0
Figure 16. Jitter Response vs. Conventional PLL
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| ADN2819ACPZ-CML-RL | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類(lèi)型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML-RL1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2820 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 制造商:Analog Devices 功能描述: |
| ADN2820S21 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
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