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參數資料
| 型號： | ADN2819ACPZ-CML1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時鐘和數據恢復芯片限幅放大器 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 570K |
| 代理商： | ADN2819ACPZ-CML1 |
ADN2819
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be
soldered directly to the ground plane to reduce series
inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias,
multiple vias may be used in parallel to reduce the series
inductance, especially on Pins 33 and 34, which are the ground
returns for the output buffers.
Rev. B | Page 17 of 24
Use of a 10 μF electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. Use of 0.1 μF and 1 nF ceramic chip capacitors should be
placed between IC power supply VCC and GND as close as
possible to the ADN2819 VCC pins. Again, if connections to the
supply and ground are made through vias, the use of multiple
vias in parallel will help to reduce series inductance, especially
on Pins 35 and 36, which supply power to the high speed
CLKOUTP/N and DATAOUTP/N output buffers. Refer to the
schematic in Figure 22 for recommended connections.
Transmission Lines
Use of 50 transmission lines are required for all high
frequency input and output signals to minimize reflections,
including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and
DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It
is also recommended that the PIN/NIN input traces are
matched in length and that the CLKOUTP/N and
DATAOUTP/N traces are matched in length. All high speed
CML outputs, CLKOUTP/N and DATAOUTP/N, also require
100 back termination chip resistors connected between the
output pin and VCC. These resistors should be placed as close
as possible to the output pins. These 100 resistors are in
parallel with on-chip 100 termination resistors to create a
50 back termination (see Figure 23).
The high speed inputs, PIN and NIN, are internally terminated
with 50 to an internal reference voltage (see Figure 24). A
0.1 μF capacitor is recommended between VREF, Pin 4, and
GND to provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to analog VCC. If vias are
used, they should be incorporated into the pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm;
the via barrel should be plated with 1 oz. copper to plug the via.
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相關代理商/技術參數 |
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| ADN2819ACPZ-CML-RL | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2820 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 制造商:Analog Devices 功能描述: |
| ADN2820S21 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
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