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參數資料
| 型號： | ADN2860 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字電位計 |
| 英文描述： | High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter; Package: MSOP; No of Pins: 10; Temperature Range: Industrial |
| 中文描述： | 250K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 512 POSITIONS, QCC24 |
| 封裝： | 4 X 4 MM, LFCSP-24 |
| 文件頁數： | 12/15頁 |
| 文件大小： | 1132K |
| 代理商： | ADN2860 |
Preliminary Technical Data
irrespective of the digital input level. In addition, there is no
polarity constraint on the voltage across terminals W and B. The
magnitude of |V
WB
| is bounded by V
DD
-V
SS
.
Power-Up Sequence
Since there are ESD protection diodes that limit the voltage
compliance at terminals A, B, and W (see figure 16), it is
important to power V
DD
/ V
SS
before applying any voltage to
terminals A, B, and W. Otherwise, the diode will be forward
biased such that V
DD
/ V
SS
will be powered unintentionally and
may affect the rest of the users’ circuit. The ideal power-up
sequence is in the following order: GND, V
DD
, V
SS
, digital
inputs, and V
A/B/W
. The order of powering V
A
, V
B
, V
W
, and
digital inputs is not important as long as they are powered after
V
DD
/ V
SS
.
Layout and Power Supply Biasing
It is always a good practice to employ compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low ESR (Equivalent Series
Resistance) 1
μ
F to 10
μ
F tantalum or electrolytic capacitors
should be applied at the supplies to minimize any transient
disturbance and filter low frequency ripple. Figure 17 illustrates
the basic supply bypassing configuration for the ADN2860.
ADN2860
Page 12 of 15
Figure 17. Power Supply Bypassing
RDAC Structure
The patent pending RDAC contains a string of equal resistor
segments, with an array of analog switches. The switches act as
the wiper connection.
The ADN2860 has two RDACs with 512 connection points
allowing it to provide better than 0.2% set-ability resolution.
The ADN2860 also contains a third RDAC with 128 step
resolution.
Figure 18 shows an equivalent structure of the connections
between the two terminals that make up one channel of an
RDAC. The SWB switch will always be ON, while on of the
switches SW(0) to SW(2N-1) will be ON at any given time
depending on the resistance position decoded from the databits
in the RDAC register.
Since the switches are non-ideal, there is a 50
wiper
resistance, R
W
. Wiper resistance is a function of supply voltage
and temperature, lower supply voltages and higher temperatures
result in higher wiper resistances. Consideration of wiper
resistance dynamics is important in applications where accurate
prediction of output resistance is required.
R
S
R
S
R
S
W
B
RDAC
WIPER
REGISTER
&
DECODER
R
S
=R
WB_FS
/2
N
SW(2
N
-1)
SW(2
N
-2)
SW(0 )
SW(1 )
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
SWB
Figure 18.. Equivalent RDAC structure
Calculating the Programmable Resistance
The nominal resistance of the RDAC between terminals A and
B is available in 25k
or 250k
. The final two or three digits of
the part number determine the nominal resistance value, e.g.
25k
= 25 and 250k
= 250.
The following discussion describes the calculation of resistance
R
WB
(D) at different codes of a 25k
part for RDAC 0. The 9-
bit data word in the RDAC latch is decoded to select one of the
512 possible settings.
The wiper first connection starts at the B terminal for data
000H. R
WB
(0) is 50
because of the wiper resistance and it is
independent to the full-scale resistance. The second connection
is the first tap point where R
WB
(1) becomes 48.8
+ 50 = 98.8
for data 001H. The third connection is the next tap point
representing R
WB
(2)=97.6+50=147.6 for data 002H and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at R
WB
(512)=25001
.
See Figure 18 for a simplified diagram of the equivalent RDAC
circuit.
The general equations that determine the programmed output
resistance between W and B are:
REV. PrD
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADN2860ACPZ25 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250 | 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250-RL7 | 功能描述:IC POT DGTL 3CH 250K 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數字電位器 系列:- 標準包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數:1 溫度系數:標準值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ADN2860ACPZ25-RL7 | 功能描述:IC POT DGTL 3CH 25K 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數字電位器 系列:- 標準包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數:1 溫度系數:標準值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ADN2860-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Channel Digital Potentiometer with Nonvolatile Memory |
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