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參數(shù)資料
| 型號： | ADP1173AR-33 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | RECTIFIER SCHOTTKY DUAL 40A 60V 375A-ifsm 0.7V-vf 1mA-ir TO-3P 30/TUBE |
| 中文描述： | 微功率DC - DC轉(zhuǎn)換 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 478K |
| 代理商： | ADP1173AR-33 |
ADP1173
–11–
REV. 0
The internal structure of the I
LIM
circuit is shown in Figure 21.
Q1 is the ADP1173’s internal power switch, which is paralleled
by sense transistor Q2. The relative sizes of Q1 and Q2 are
scaled so that I
Q2
is 0.5% of I
Q1
. Current flows to Q2 through an
internal 80
resistor and through the R
LIM
resistor. These two
resistors parallel the base-emitter junction of the oscillator-
disable transistor, Q3. When the voltage across R1 and R
LIM
exceeds 0.6 V, Q3 turns on and terminates the output pulse. If
only the 80
internal resistor is used (i.e., the I
LIM
pin is con-
nected directly to V
IN
), the maximum switch current will be
1.5 A. Figures 4 and 5 gives R
LIM
values for lower current-limit
values.
OSCILLATOR
V
IN
SW2
SW1
R
LIM
DRIVER
80
(INTERNAL)
I
LIM
(EXTERNAL)
Q2
Q1
Q3
R1
Figure 21. Current Limit Operation
The delay through the current limiting circuit is approximately
2
μ
s. If the switch ON time is reduced to less than 4
μ
s, accu-
racy of the current trip-point is reduced. Attempting to program
a switch ON time of 2
μ
s or less will produce spurious responses
in the switch ON time. However, the ADP1173 will still provide
a properly regulated output voltage.
PROGRAMMING THE GAIN BLOCK
The gain block of the ADP1173 can be used as a low-battery
detector, error amplifier or linear post regulator. The gain block
consists of an op amp with PNP inputs and an open-collector
NPN output. The inverting input is internally connected to the
ADP1173’s 1.245 V reference, while the noninverting input is
available at the SET pin. The NPN output transistor will sink
about 100
μ
A.
2
V
IN
+5V
GND
ADP1173
R1
AO
SET
5
R2
100k
TO
PROCESSOR
6
1.245V
REF
7
V
BAT
V
LB
–1.245V
12.5μA
V
LB
= BATTERY TRIP POINT
R2 = 100k
R1 =
Figure 22. Setting the Low Battery Detector Trip Point
Figure 22 shows the gain block configured as a low battery
monitor. Resistors R1 and R2 should be set to high values to
reduce quiescent current, but not so high that bias current in the
SET input causes large errors. A value of 100 k
for R2 is a
good compromise. The value for R1 is then calculated from the
formula:
R
1
=
V
LOBATT
1.245
V
1.245
V
R
2
where V
LOBATT
is the desired low battery trip point. Since the
gain block output is an open-collector NPN, a pull-up resistor
should be connected to the positive logic power supply.
2
V
IN
5V
GND
ADP1173
R1
AO
SET
5
R2
47k
TO
PROCESSOR
6
1.245mV
REF
7
V
BAT
R3
1.6M
Figure 23. Adding Hysteresis to the Low Battery Detector
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