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參數資料
| 型號： | ADP3156JR-18 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Power Supply Controller for Desktop Systems |
| 中文描述： | 雙電源控制器桌面系統 |
| 文件頁數： | 9/12頁 |
| 文件大小： | 186K |
| 代理商： | ADP3156JR-18 |
REV. 0
ADP3156
–9–
current of 1.7 A and an average short-circuit current of about
6.5 A—meaning that there is actually a small degree of short-
circuit current foldback. To safely carry the maximum current,
the sense resistor must have a power rating of at least (11.2 A –
1.07 A)
2
×
12.9 mW = 1.3 W.
Current Transformer Option
An alternative to using a low value and high power current sense
resistor is to reduce the sensed current by using a low cost cur-
rent transformer and a diode. The current can then be sensed
with a small size, low cost SMT resistor. Using a transformer
with one primary and 50 secondary turns reduces the worst-case
resistor dissipation to a few mW. Another advantage of using
this option is the separation of the current and voltage sensing,
which makes the voltage sensing more accurate.
Power MOSFETs
Two external N-channel power MOSFETs must be selected for
use with the ADP3156, one for the main switch, and an identi-
cal one for the synchronous switch. The main selection param-
eters for the power MOSFETs are the threshold voltage V
GS(TH)
and the on resistance R
DS(ON)
. The minimum input voltage
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. For V
IN
> 8 V, standard threshold
MOSFETs (V
GS(TH)
< 4 V) may be used. If V
IN
is expected to
drop below 8 V, logic-level threshold MOSFETs (V
GS(TH)
<
2.5 V) are strongly recommended. Only logic-level MOSFETs
with V
GS
ratings higher than the absolute maximum of V
CC
should be used.
The maximum output current I
OMAX
determines the R
DS(ON)
requirement for the two power MOSFETs. When the ADP3156
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. For V
IN
= 5 V and V
OUT
= 1.8 V, the
maximum duty ratio of the high side FET is:
D
MAXHF
= (1 –
f
MIN
×
t
OFF
) = (1 – 150
kHz
×
3.2
μ
s
) = 52%
The duty ratio of the low side (synchronous rectifier) FET un-
der the maximum load condition is:
D
MAXLF
= 1 –
D
MAXHF
= 48%
The maximum rms current of the high side FET is:
I
RMSHS
= [
D
MAXHF
(
I
LVALLEY
2 +
I
LPEAK
2 +
I
LVALLEY
I
LPEAK
)/3]
0.5
= 7.32
A rms
The maximum rms current of the low side FET is:
I
RMSLS
= [
D
MAXLF
(
I
LVALLEY
2 +
I
LPEAK
2 +
I
LVALLEY
I
LPEAK
)/3]
0.5
= 7.03
A rms
The R
DS(ON)
for each FET can be derived from the allowable
dissipation. Allowing 8% of the maximum output power for
FET dissipation, the total dissipation will be:
P
FETALL
= 0.08
V
O
I
OMAX
= 1.0
W
Allocating half of the total dissipation for the high side FET and
half for the low side FET, the required minimum FET resis-
tances will be:
R
DS(ON)HSF(MIN)
= 1
W
×
52%/(7.32A)
2
= 9.7 m
R
DS(ON)LSF(MIN)
= 1
W
×
48%/(7.03A)
2
= 9.7 m
Note that there is a trade-off between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is
not a major concern, the International Rectifier IRL3103 is an
economical choice for both the high side and low side positions.
Those devices have an R
DS(ON)
of 14 m
at V
GS
= 10 V and at
+25
°
C. The low side FET is turned on with at least 10 V. The
high side FET, however, is turned on with only 12 V – 5 V =
7 V. Checking the typical output characteristics of the device in
the data sheet, shows that for an output current of 10 A, and at
a V
GS
of 7 V, the V
DS
is 0.15 V. This gives an R
DS(ON)
only
slightly above the one specified at a V
GS
of 10 V, so the resis-
tance increase due to the reduced gate drive can be neglected.
The specified R
DS(ON)
at the expected highest FET junction
temperature of +140
°
C must be modified by an R
DS(ON)
multi-
plier, using the graph in the data sheet. In this case:
R
DS(ON)MULT
= 1.7
Using this multiplier, the expected R
DS(ON)
at +140
°
C is
1.7
×
14 = 24 m
.
The high side FET dissipation is:
P
DFETHS
=
I
RMSHS
2
R
DS(ON)
+ 0.5
V
IN
I
LPEAK
Q
G
f
MIN
/
I
G
~ 2.54
W
where the second term represents the turn-off loss of the FET.
(In the second term, Q
G
is the gate charge to be removed from
the gate for turn-off and I
G
is the gate current. From the data
sheet, Q
G
is about 50 nC–70 nC and the gate drive current
provided by the ADP3156 is about 1 A.)
The low side FET dissipation is:
P
DFETLS
=
I
rmsls
2
R
DS
(
ON
)
= 0.49
W
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinking should be used. The heat sink and airflow
are chosen based on how low the impedance must be reduced in
order to keep the MOSFET’s junction temperature at an ac-
ceptably low level, according to the formula:
θ
HA
= [(
T
J
MAXOP
–
T
A
)
P
DFET
] –
θ
J
C
–
θ
CH
where
θ
HA
is the thermal resistance from the heat sink to ambi-
ent air (and depends on airflow),
T
J
MAXOP
is the user-deter-
mined maximum acceptable operating temperature of the
MOSFET, and the last two factors are the thermal resistance
from junction-to-case of the device, and case-to-heat sink. Typi-
cally, the junction-to-case thermal resistance is 2
°
C/W, and the
case-to-heat sink resistance is 0.5
°
C/W.
C
IN
Selection and Input Current di/dt Reduction
In continuous-inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V
O
/V
lN
.
To keep the input ripple voltage at a low value, one or more
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass ca-
pacitors is:
I
CINRMS
=
I
OMAX
[
D
MAX
×
(1–
D
MAX
)]
0.5
= 3.5 A
For an FA-type capacitor with 2700 mF capacitance and 10 V
voltage rating, the ESR is 34 m
and the allowed ripple current
at 100 kHz (and similar frequencies) is 1.94 A. At +105
°
C, two
such capacitors may be connected in parallel to handle the cal-
culated ripple current.
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/
μ
s, an additional
small inductor should be inserted between the converter and the
supply bus (see Figure 2).
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