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參數資料
| 型號： | ADP3163JRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 138K |
| 代理商： | ADP3163JRU |
REV. 0
ADP3163
–10–
At output voltages below 750 mV, the current sense threshold is
reduced to 108 mV, and the ripple current is negligible. There-
fore, at dead short the output current is reduced to:
I
n
V
R
mV
m
A
OUT SC
CS SC
(
SENSE
(
)
)
=
×
=
×
=
3
108
5
65
(5)
To safely carry the current under maximum load conditions, the
sense resistor must have a power rating of at least:
P
I
R
R
SENSE RMS
SENSE
SENSE
=
×
(
)
2
(6)
where:
I
I
n
V
η
V
SENSE RMS
O
OUT
×
IN
(
)
2
2
=
×
(7)
In this formula,
n
is the number of phases, and
η
is the con-
verter efficiency, in this case assumed to be 85%. Combining
Equations 6 and 7 yields:
P
A
V
V
m
W
R
SENSE
=
×
×
=
65
3
1 5
.
0 85 12
.
5
1 0
.
2
Output Resistance
This design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance of:
R
V
V
I
V
V
A
m
OUT
ONL
OFL
O
=
=
=
1 475
.
1 377
.
65
1 5
.
(8)
The required dc output resistance can be achieved by terminating
the g
m
amplifier with a resistor. The value of the total termina-
tion resistance that will yield the correct dc output resistance:
R
n
×
R
n
g
R
m
×
mmho
m
k
T
I
SENSE
×
m
OUT
=
×
=
1 5
.
×
=
12 5 5
2 2
.
3
6 31
.
.
(9)
where
n
I
is the division ratio from the output voltage signal of the
g
m
amplifier to the PWM comparator CMP1,
g
m
is the transcon-
ductance of the g
m
amplifier itself, and
n
is the number of phases.
Output Offset
Intel’s specification requires that at no load the nominal output
voltage of the regulator be offset to a lower value than the nominal
voltage corresponding to the VID code. The offset is introduced
by realizing the total termination resistance of the g
m
amplifier
with a divider connected between the REF pin and ground. The
resistive divider introduces an offset to the output of the g
m
amplifier that, when reflected back through the gain of the g
m
stage, accurately positions the output voltage near its allowed
maximum at light load. Furthermore, the output of the g
m
amplifier sets the current sense threshold voltage. At no load,
the current sense threshold is increased by the peak of the ripple
current in the inductor and reduced by the delay between sens-
ing when the current threshold has been reached and when the
high side MOSFET actually turns off. These two factors are
combined with the inherent voltage (V
GNL0
), at the output of the
g
m
amplifier that commands a current sense threshold of 0 mV:
V
V
I
R
n
V
V
L
n
t
R
n
V
V
A
m
2
V
600
V
nH
ns
m
V
GNL
GNL
L(
SENSE
I
IN
OUT
D
SENSE
I
GNL
=
+
×
×
×
×
×
×
=
+
×
×
×
×
×
×
=
0
2
1
10 9
5
12 5
12
1 5
.
2
60
5
12 5
1 144
.
)
.
.
.
(10)
The divider resistors (R
A
for the upper and R
B
for the lower)
can now be calculated, assuming that the internal resistance of
the g
m
amplifier (R
OGM
) is 1 M
:
R
V
V
V
R
g
V
V
R
V
V
V
k
mmho
V
V
k
B
REF
REF
GNL
T
m
ONL
VID
B
=
×
=
.
×
=
(
)
.
.
( .
1 475
.
)
.
3
3
1 144
6 31
2 2
1 5
8 59
(11)
Choosing the nearest 1% resistor value gives R
B
= 8.66 k
.
Finally, R
A
is calculated:
Choosing the nearest 1% resistor value gives R
A
= 23.7 k
.
C
OUT
Selection
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR must be less than or equal to the specified output
resistance (R
OUT
), in this case 1.5 m
. The capacitance must be
large enough that the voltage across the capacitors, which is the
sum of the resistive and capacitive voltage deviations, does not
deviate beyond the initial resistive step while the inductor cur-
rent ramps up or down to the value corresponding to the new
load current.
One can, for example, use nine MBZ-type capacitors from
Rubycon, with 2200
μ
F capacitance, a 6.3 V voltage rating, and
13 m
ESR. The nine capacitors have a maximum total ESR of
1.44 m
when connected in parallel.
As long as the capacitance of the output capacitor bank is above
a critical value and the regulating loop is compensated with
Analog Devices’ proprietary compensation technique (ADOPT),
the actual capacitance value has no influence on the peak-to-
peak deviation of the output voltage to a full step change in the
load current. The critical capacitance can be calculated as follows:
R
R
R
R
k
M
k
k
A
T
OGM
B
=
=
=
1
1
1
1
1
1
1
6 31
.
1
1
8 66
.
23 8
.
(12)
1 5
C
I
R
V
L
n
A
×
m
V
nH
3
mF
OUT CRIT
(
O
×
OUT
OUT
)
.
.
.
=
×
=
×
=
65
1 5
600
5 78
(13)
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