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參數資料
| 型號： | ADP3163JRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 138K |
| 代理商： | ADP3163JRU |
REV. 0
ADP3163
–12–
Allocating half of the total dissipation for the four high-side
MOSFETs and half for the four low-side MOSFETs, and
assuming that the resistive and switching losses of the high-side
MOSFETs are equal, the required maximum MOSFET resis-
tances will be:
R
P
n
I
W
.
7 7
A
m
DS ON HSF
(
FET TOTAL
(
×
HSF MAX
(
)
)
)
.
.
=
×
=
×
×
=
4
9 06
3
4
12 7
2
2
(21)
and:
R
P
n
I
W
.
A
m
DS ON LSF
(
FET TOTAL
(
×
LSF MAX
(
)
)
)
.
×
.
=
×
=
×
=
2
9 06
3
2
20 4
3 63
2
2
(22)
Note that there is a trade-off between converter efficiency and
cost. Larger MOSFETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. A Fairchild
FDB7030L (R
DS(ON)
= 7 m
nominal, 10 m
worst-case) for
the high-side and a Fairchild FDB8030L (R
DS(ON)
= 3.1 m
nominal, 5.6 m
worst-case) for the low-side are good choices.
The high-side MOSFET dissipation is:
P
V
R
I
I
Q
f
I
V
Q
f
m
A
V
A
nC
A
W
kHz
V
nC
kHz
HSF
DS ON HSF
×
×
2
HSF MAX
(
IN
L PK
(
G
SW
G
IN
RR
SW
=
×
×
×
+
×
×
=
×
+
×
×
2 1
2 17
×
+
×
×
=
(
)
)
)
.
.
2
2
10
7 7
12
29
35
200
12
150
200
(23)
Where the first term is the conduction loss of the MOSFET, the
second term represents the turn-off loss of the MOSFET and
the third term represents the turn-on loss due to the stored
charge in the body diode of the low-side MOSFET. In the sec-
ond term, Q
G
is the gate charge to be removed from the gate for
turn-off and I
G
is the gate turn-off current. From the data sheet,
for the FDB7030L the value of Q
G
is about 35 nC and the peak
gate drive current provided by the ADP3414 is about 1 A. In
the third term, Q
RR
, is the charge stored in the body diode of
the low-side MOSFET at the valley of the inductor current. The
data sheet of the FDB8030L does not give that information, so
an estimated value of 150 nC is used. This estimate is based on
information found on data sheets of similar devices. In both
terms, f
SW
is the actual switching frequency of the MOSFETs,
or 200 kHz. I
L(PK)
is the peak current in the inductor, or 27 A.)
The worst-case low-side MOSFET dissipation is:
P
Note that there are no switching losses in the low-side MOSFET.
R
I
m
A
W
LSF
DS ON LSF
(
LSF MAX
(
=
×
=
×
=
)
)
.
.
.
2
2
5 6
20 4
2 33
(24)
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to V
OUT
/V
IN
and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
I
I
n
n
D
n
D
A
A
C(
O
HSF
HSF
)
(
)
.
(
.
)
.
=
×
×
×
=
×
×
×
=
2
2
65
3
3
0 125
3
0 125
10 5
(25)
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 270
μ
F, 16 V OS-CON capacitors with a ripple current
rating of 4.4 A each.
The ripple voltage across the three paralleled capacitors is:
V
I
n
+
ESR
n
D
C
n
f
A
m
3
F
kHz
mV
C RIPPLE
(
O
C
C
HSF
C
IN
SW
=
)
.
=
×
+
×
×
=
×
×
×
65
3
18
0 125
μ
3
270
200
147
(26)
Multilayer ceramic input capacitors are also required. These
capacitors should be placed between the input side of the cur-
rent sense resistor and the sources of the low side synchronous
MOSFETS. These capacitors decouple the high frequency leading
edge current spike which supplies the reverse recovery charge of the
low side MOSFETS body diode. The exact number required is a
function of board layout. Typical designs will use two 10
μ
F
MLC capacitors.
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/
μ
s, an additional small inductor (L > 1
μ
H
@ 15 A) should be inserted between the converter and the sup-
ply bus. That inductor also acts as a filter between the converter
and the primary power source.
+
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