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參數(shù)資料
| 型號(hào)： | ADP3163JRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 138K |
| 代理商： | ADP3163JRU |
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REV. 0
ADP3163
–4–
PIN FUNCT ION DE SCRIPT IONS
Pin
Name
Function
1–5
VID4 –
VID0
Voltage Identification DAC Inputs. These pins are pulled up to an internal 3 V reference, providing a
Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.1 V to 1.85 V. Leaving all five
DAC inputs open results in the ADP3163 going into a “No CPU” mode, shutting off its PWM outputs.
Current Sharing Output. This pin is connected to the SHARE pins of other ADP3163s in multiple VRM sys-
tems to ensure proper current sharing between the converters. The voltage at this output programs the output
current control level between CS+ and CS–.
Error Amplifier Output and Compensation Point.
Ground. FB, REF and the VID DAC of the ADP3163 are referenced to this ground. This is a low current ground
that can also be used as a return for the FB pin in remote voltage sensing applications.
Feedback Input. Error amplifier input for remote sensing of the output voltage.
External capacitor CT connection to ground sets the frequency of the device.
Open drain output that signals when the output voltage is outside of the proper operating range or when a phase
is not supplying current even if the output voltage is in specification.
Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a volt-
age at this pin with respect to CS–.
Current Sense Negative Node. Negative input for the current comparator.
Power Ground. All internal biasing and logic output signals of the ADP3163 are referenced to this ground.
Phase Control Input. This logic-level input determines the number of active phases and the duty cycle limit of
each phase.
Logic-Level Output for the Phase 3 Driver.
Logic-Level Output for the Phase 2 Driver.
Logic-Level Output for the Phase 1 Driver.
3.0 V Reference Output.
Supply Voltage for the ADP3163.
6
SHARE
7
8
COMP
GND
9
10
11
FB
CT
PWRGD
12
CS+
13
14
15
CS–
PGND
PC
16
17
18
19
20
PWM3
PWM2
PWM1
REF
VCC
5-BIT CODE
VID4
VID3
VID2
VID1
VID0
SHARE
COMP
GND
FB
CT
VCC
REF
PWM1
PWM2
PWM3
PC
PGND
CS
–
CS+
PWRGD
3
1
4
5
18
17
16
2
20
19
6
10
7
8
9
11
14
13
12
15
ADP3163
12V
100
100nF
1.2V
1 F
100nF
V
FB
20k
AD820
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
T able I. PWM Outputs vs. Phase Control Code
Maximum
Duty Cycle
PC
PWM3
PWM2
PWM1
REF
GND
ON
OFF
ON
ON
ON
ON
33%
50%
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