
REV. 0
–14–
ADP3166
In this example,
L
X
is 375 pH for the eight OSCON capacitors,
which basically satisfies this limitation. If the
L
X
of the chosen
bulk capacitor bank is too large, the number of capacitors must
be increased.
One should note for this multimode control technique, all-
ceramic designs can be used as long as the conditions of
Equations 12, 13, and 14 are satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
, and R
DS(ON)
. The minimum gate
d
rive voltage (the supply voltage to the ADP3418) dictates
whether standard threshold or logic-level threshold MOSFETs
must be used. With V
GATE
~10 V, logic-level threshold MOSFETs
(V
GS(TH)
< 2.5 V) are recommended.
The maximum output current, I
O
, determines the R
DS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3166, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (
n
SF
). With conduction losses
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (
I
R
) and average total output current (
I
O
):
P
=
– D
I
n
+
n
I
n
R
SF
O
SF
R
SF
DS SF
1
(
1
12
2
2
)
×
×
×
×
)
(15)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the required
R
DS(ON)
for the MOSFET. For D-PAK MOSFETs up to an
ambient temperature of 50oC, a safe limit for P
SF
is 1 W to 1.5 W
at 120oC junction temperature. Thus, for our example (56 A
maximum), we find R
DS(SF)
(per MOSFET) < 10 m
. This
R
DS(SF)
is also at a junction temperature of about 120oC, so we
need to make sure we account for this when making this selection.
For our example, we selected two lower-side MOSFETs at 7 m
each at room temperature, which gives 8.4 m
at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and the feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch off the synchronous MOSFETs should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is about 2
and the typical MOSFET input gate resistances
are about 1
to 2
, so a total gate capacitance of less than
6000 pF should be adhered to. Since there are two MOSFETs in
parallel, we should limit the input capacitance for each synchro-
nous MOSFET to 3000 pF.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switch-
ing speed on the rise and fall time of the gate driver impedance
and MOSFET input capacitance, the following expression pro-
vides an approximate value for the switching loss per main
MOSFET, where
n
MF
is the total number of main MOSFETs:
P
= 2
f
V
I
n
R
n
n
C
S MF
SW
CC
O
MF
G
MF
ISS
)
×
×
×
×
×
×
(16)
Here,
R
G
is the total gate resistance (2
for the ADP3418 and
about 1
for typical high speed switching MOSFETs, making
R
G
= 3
) and
C
ISS
is the input capacitance of the main
MOSFET. It is interesting to note that adding more main
MOSFETs (
n
MF
) does not really help the switching loss per
MOSFET since the additional gate capacitance slows down
switching. The best thing to reduce switching loss is to use
lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the fol-
lowing, where RDS(MF) is the on resistance of the MOSFET:
P
= D
I
n
+
n
I
n
R
C MF
O
MF
R
MF
DS MF
)
)
×
×
×
×
2
2
1
12
(17)
Typically, for main MOSFETs, one wants the highest speed
(low C
ISS
) device, but these usually have higher on resistance.
One must select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the switch-
ing and conduction losses.
For our example, we have selected an Infineon IPD12N03L as
the
main MOSFET (three total; n
MF
= 3), with a C
ISS
= 1460 pF (max)
and R
DS(MF)
= 14 m
(max at T
J
= 120oC) and an Infineon
IPD06N03L as the synchronous MOSFET (six total; n
SF
= 6),
with C
ISS
= 2370 pF (max) and R
DS(SF)
= 8.4 m
(max at T
J
= 120oC).
The synchronous MOSFET CISS is less than 3000 pF, satisfy-
ing that requirement. Solving for the power dissipation per
MOSFET at I
O
= 56 A and I
R
= 6.6 A yields 647 mW for each
synchronous MOSFET and 1.26 W for each main MOSFET.
These numbers work well considering there is usually more
PCB area available for each main MOSFET versus each syn-
chronous MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for the
MOSFETs and is given by the following, where
Q
GMF
is the
total gate charge for each main MOSFET and
Q
GSF
is the total
gate charge for each synchronous MOSFET:
P
=
f
n
n
Q
+n
Q
+ I
V
DRV
SW
2
×
MF
GMF
SF
GSF
CC
CC
×
×
×
(
)
(18)
Also shown is the standby dissipation factor (
I
CC
V
CC
) for the
driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. For our example, with
I
CC
= 7 mA,
Q
GMF
=
22.8 nC and
Q
GSF
= 34.3 nC, we find 265 mW in each driver,
which is below the 400 mW dissipation limit. See the ADP3418
data sheet for more details.