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參數資料
| 型號： | ADP3166 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 5位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 351K |
| 代理商： | ADP3166 |
REV. 0
ADP3166
–7–
THEORY OF OPERATION
The ADP3166 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and 4-phase
synchronous buck CPU core supply power converters. The
internal 5-bit VID DAC conforms to AMD’s Hammer family
power specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single-
phase converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.
The multimode control of the ADP3166 ensures a stable, high
performance topology for
Balancing currents and thermals between phases.
High speed response at the lowest possible switching frequency
and output decoupling.
Minimizing thermal switching losses due to lower frequency
operation.
Tight load line regulation and accuracy.
High current output from having up to 4-phase operation.
Reduced output ripple utilizing multiphase cancellation.
Immunity to board layout.
Ease of use and design due to independent component
selection.
Flexibility in operation for tailoring design to low cost or
high performance.
Number of Phases
The number of operational phases and their phase relationship
are determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3166 operates as a 4-phase PWM
controller. Grounding the PWM 4 pin programs 3-phase opera-
tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.
When the ADP3166 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An inter-
nal comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, it will be below the threshold
and the phase will be disabled. The output impedance of the
PWM pin is approximately 5 k
. Any external pull-down resis-
tance connected to the PWM pin should not be less than 25 k
to ensure proper operation. The phase detection is made during
the first two clock cycles of the internal oscillator. After this
time, if the PWM output was not grounded, it will switch between
0 V and 5 V. If the PWM output was grounded, it will remain off.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
Master Clock Frequency
The clock frequency of the ADP3166 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the frequency
of the remaining phases. If PWM3 and PWM4 are grounded,
divide by 2. If all phases are in use, divide by 4.
Table I. VID Code vs. Output Voltage
VID3
VID2
VID1
VID4
VID0
V
OUT(NOM)
(V)
No CPU
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Output Voltage Differential Sensing
The ADP3166 combines differential sensing with a high accu-
racy VID DAC and reference and a low offset error amplifier to
maintain a worst-case specification of
±
1% differential sensing
error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micropro-
cessor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision refer-
ence are referenced to FBRTN, which has a minimal current of
100
μ
A to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
Output Current Sensing
The ADP3166 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current, and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
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相關代理商/技術參數 |
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| ADP3166JRU-REEL | 功能描述:IC REG BUCK 5BIT 2-4PHAS 28TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ADP3166JRU-REEL7 | 功能描述:IC REG BUCK 5BIT 2-4PHAS 28TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ADP3166JRUZ-REEL | 功能描述:IC REG BUCK 5BIT 2-4PHAS 28TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ADP3167 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADP3160/ADP3167: 5-Bit Programmable 2-Phase Synchronous Buck Controller Data Sheet (Rev. B. 5/02) |
| ADP3167JR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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