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參數(shù)資料
| 型號(hào)： | ADP3502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | CDMA Power Management System |
| 中文描述： | CDMA的電源管理系統(tǒng) |
| 文件頁數(shù)： | 23/36頁 |
| 文件大小： | 714K |
| 代理商： | ADP3502 |
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REV. 0
ADP3502
–23–
Table III. Setup and Hold Specifications
Parameter
*
Min
Typ
Max
Unit
Test Condition/Comments
t
CKS
t
CSS
t
CKH
t
CKL
t
CSH
t
CSR
t
DS
t
DH
t
RD
t
RZ
t
CSZ
50
50
100
100
100
62
50
40
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
CLK Setup Time
CS Setup Time
CLK High Duration
CLK Low Duration
CS Hold Time
CS Recovery Time
Input Data Setup Time
Input Data Hold Time
Data Output Delay Time
Data Output Floating Time
Data Output Floating Time after CS Goes Low
50
50
50
*
These parameters are not tested.
Function Block
The ADP3502 integrates the serial bus interface for easy com-
munication with the system. The data bus consists of three
wires (CLK, CS, and DATA) and is capable of serial-to-
parallel/parallel-to-serial conversion of data, as well as clock
transfer.
Serial interface block works during the time period at CS signal
enable. After the falling edge of CLKIN, signals right after the
rising edge of the CS signal, address, transfer control signal,
and write data are held in sequentially. In case of DATA READ,
data will be prepared by the rising edge of CLKIN, and the base-
band chip may want to read or latch the data at the falling
edge of CLKIN. While CS is not asserted, CLKIN is ignored.
If CS goes “L” while CLKIN is continuously applied or input
DATA, all data is canceled, and the DATA line would be high
impedance. In this case, users need to input the data again.
Note that CLKIN should stay “L” when CS goes “H.” RTC
counter registers should be accessed at a certain time (>62
μ
s) after
CS assertion. Asserting RESETIN N (RESETIN–), signal
resets the block.
Notes:
CLKIN should be “L” when CS goes “H.”
In case of RTC counter access, the access should be approxi-
mately 62
μ
s (two clock cycles of CLK32K) after the CS signal
is asserted to hold the RTC value.
The CS should not be asserted for 62
μ
s (2 clock cycles of
CLK32K) after the CS is released.
CS signal should never be asserted for 1 sec or longer; other-
wise the RTC counter makes an error.
CLKIN should be chosen as a multiple of 16 if CS < 31
μ
s.
DATAIN
RW SEL
RESETIN N
CS
CLKIN
DATA
PARALLEL-TO-SERIAL
CONVERSION
PS DATA [7:0]
SP ADDR [5:0]
WRITE ENABLE
CREATION OF
WRITE DATA
SP DATA [7:0]
SYNCHRONIZATION
AND DATA SELECTION
SERIAL-TO-PARALLEL
CONVERSION
Figure 8. Serial Interface Block Diagram
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| ADP3502ASU | CDMA Power Management System |
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| ADP3510ARU | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.40V) 8-SM8 -40 to 110 |
| ADP3522 | GSM Power Management System |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP3502ASU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3502ASU-REEL | 制造商:Analog Devices 功能描述:CDMA Power Management System 64-Pin TQFP T/R |
| ADP3510 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU-REEL7 | 制造商:Analog Devices 功能描述: |
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