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參數資料
| 型號： | ADP3502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | CDMA Power Management System |
| 中文描述： | CDMA的電源管理系統 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 714K |
| 代理商： | ADP3502 |
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REV. 0
ADP3502
–27–
RTC Block
The calendar registers are set through the serial interface.
Function
RTC counter using binary
Reading out and writing settings of year, month, day, week,
hour, minute, and second data
Leap year controls, number of days in a month control
Alarm function (week, hour, minute)
Periodic interrupt function—2 Hz, 1 Hz, 1/60 Hz, 1/3600 Hz,
each month (first day of each month)
Protection of wrong data readout during RTC data update
Operation
Synchronizing with the RTC CLK32K clock, the USEC counter
generates a 1 sec timing clock, which hits the RTC counter.
Through the serial interface, the CPU can write the setting
value and read the RTC counter value. In case the RTC counter
toggles during the serial interface access to the RTC counter,
the wrong data can be read/written between the RTC counter
and the interface. The CS signal stops the clocking to the RTC
counter until the CS signal is released. In case the CPU writes
data into the SEC counter, the USEC counter is reset to zero.
Note the following:
In case of RTC counter access, the access should wait approxi-
mately 62
μ
s, (two clock cycles of CLK32K) after the CS signal
is asserted, to hold the RTC value.
The CS signal should never be asserted 1 sec or longer since
this effects counter operation.
USEC Counter Operation
The USEC counter counts up synchronizing with the
RTC CLK32K clock. It generates a 1 sec timing signal and is
used as an increment clocking of the RTC counter. In case the
1 sec signal is generated during the CS signal asserted, the incre-
ment clock is delayed until the CS signal is released.
RTC Counter Operation
The RTC counter uses the increment signal from the USEC
counter to control the counting operation, including the leap
year control and numbers of days in a month control.
RTC CLK32K
RTC SP ADDR [5:0]
RTC WRITE ENABLE
RTC WRITE DATA [7:0]
(FROM SERIAL I/F)
RTC CS
RESET WILL BE ASSERTED WHEN
RTC COUNTER IS WRITTEN.
REGISTERS FOR
TEST MODE
RESET TO RTC AND USEC COUNTERS
WRITE INITIAL DATA OF USEC COUNTER
RTC
REGISTER
BLOCK
RTC
COUNTER
LEAND
CDATE
USEC
COUNTER
SEC COUNTER
INCREMENT
CONTROL
ALARM
COMPARATOR
PERIODIC
INTERRUPT
DATA
SELECT
RTC ALARM INT
RTC CTFG INT
RTC DATA [7:0]
LOADING
ALARM
TIMES
Figure 13. RTC Counter Block
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADP3502ASU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3502ASU-REEL | 制造商:Analog Devices 功能描述:CDMA Power Management System 64-Pin TQFP T/R |
| ADP3510 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU-REEL7 | 制造商:Analog Devices 功能描述: |
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