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參數資料
| 型號： | ADP3502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | CDMA Power Management System |
| 中文描述： | CDMA的電源管理系統 |
| 文件頁數： | 28/36頁 |
| 文件大小： | 714K |
| 代理商： | ADP3502 |
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REV. 0
–28–
ADP3502
LEAP YEAR
AND
DAYS IN MONTH
CONTROL
YEAR COUNT
MONTH COUNT
DAY COUNT
WEEK COUNT
HOUR COUNT
MIN COUNT
SEC COUNT
ENABLED SIGNALS
CREATED
BY DECODING OF
RTC SP ADDR [5:0]
ADDR 06h WRITE
ADDR 00h WRITE
INITIAL DATA
INC ENB
INC CLK
USEC
COUNTER
YEAR
06h
100 SCALE
MONTH
05h
12 SCALE
DATE
04h
31 SCALE
WEEK
03h
7 SCALE
HOUR
02h
12 SCALE
MINUTE
01h
60 SCALE
SECOND
00h
60 SCALE
TO
FOLLOWING
COUNTERS
Figure 14. RTC Counter Block Diagram
Periodic Interrupt Function
This function generates interrupt periodically. The timing of
the cycle can be selected from 2 Hz (0.5 sec clock pulse), 1 Hz
(1 sec clock pulse), 1/60 Hz (minutes), 1/3600 Hz (hour), and
month (first day of each month).
The cycle is set using the PI2–PI0 value in the periodic interrupt
control, PIC register (0Eh). The state when interrupt is gener-
ated is indicated at the INTRA bit of PIC register (0Eh). The
INT MASK register (1Fh) only masks the periodic interrupt
signal. There are two periodic interrupt signal output patterns:
1. Hold the value when the interrupt occurs (level).
2. After the interrupt event happens, assert the interrupt signal
in a certain time period and then release it (pulse).
In level case, interrupt occurs at each 0 min (1/60 Hz), 0 o’clock
(1/3600 Hz), or the first day of the month. Because they
happen in long cycles, the value is held at the register. After the
CPU checks the state, it is released by writing a “1” to the PIC
Bit of the PIC Register. If 2 Hz and 1 Hz, the interrupt is not
held because the event happens in short cycles. These event
signals output the pulse signal 2 Hz or 1 Hz in the RTC counter
directly. The interrupt release operation doesn’t affect the inter-
rupt signal in this case.
Stay-Alive Timer
This is a counter that increments each 250 ms after
RTC RESETIN N is asserted. It holds its value when the counter
counts full up. Signal CLK4 is a 4 Hz (250 ms) clock that was
generated in the USEC counter. The counter can be reset by
writing a “1” at the CLR of the Stay-Alive TIMER CONTROL
register (0Fh). The RTC RESETIN N signal is transferred from a
logic input circuit that is supplied by VBAT of RESETIN N.
Note: Users just need to write a “1” to release the interrupt and
do not need to write a “0” after the “1.”
Definition of Leap Year
For this device, the following definition of a leap year is used instead:
“A year that can be divided by 4.”
Note:
Year counter = “00” means year 2000 and is a leap year,
because it can be divided by 400.
Actual covered year period is from 1901 to 2099.
Number of Days of Month Control
Months 1, 3, 5, 7, 8, 10, and 12 have 31 days.
Months 4, 6, 9, and 11 have 30 days.
Month 2 has 28 days but has 29 days in a leap year.
Alarm Function
Comparing the RTC counter value with the setting value in the
alarm setting register (07h–09h), the alarm condition is de-
tected. Setting of week uses seven bits for each day of the
week and works with multiple day settings. There is a delay of
62
μ
s from alarm detection to setting up the AOUT/BOUT
registers.
The ALA EN flag in the ALARM CONTROL register (0Dh)
sets the enable/disable of the alarm detection. The INT register
(1Eh) indicates the interrupt signals, ALARM INT of ALA or/
and ALB. The INT MASK register (1Fh) does mask the
alarm interrupt signal. The alarm detection state is indicated as
AOUT of the ALARM CONTROL register (0Dh), and the
alarm can be released by writing a “1” at the bit. Alarm B is
controlled the same as Alarm A.
Note: Users just need to write a “1” to release the alarm and do
not need to write a “0” after the “1.” Users do not need to wait
62
μ
s from CS assertion.
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