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參數資料
型號: ADP3808JCPZ-RL
廠商: ANALOG DEVICES INC
元件分類: 穩壓器
英文描述: High Efficiency Switch Mode Li-Ion Battery Charger
中文描述: BATTERY CHARGE CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, QCC24
封裝: ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24
文件頁數: 12/16頁
文件大小: 315K
代理商: ADP3808JCPZ-RL
ADP3808
Rev. 0 | Page 12 of 16
MIN
OFF
TIME
DRVREG
BST
DRVH
SW
IN
DRVL
CBST
PGND
1V
1V
Q1
Q2
DELAY
DRVLSD
EN
DELAY
CMP3
CMP2
CMP1
+
+
ADP3808
BOOTSTRAPPED
SYNCHRONOUS DRIVER
0
Figure 17. Bootstrapped Synchronous Driver
5.25 V BOOTSTRAP REGULATOR
The driver stage is powered by the internal 5.25 V bootstrap
regulator, which is available at the DRVREG pin. Because the
switching currents are supplied by this regulator, decoupling
must be added. A 0.1 μF capacitor should be placed close to the
ADP3808, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
BOOTSTRAPPED SYNCHRONOUS DRIVER
The PWM comparator controls the state of the synchronous
driver shown in Figure 17. A high output from the PWM
comparator forces DRVH on and DRVL off. The drivers have
an on resistance of less than 4 Ω for fast rise and fall times when
driving external MOSFETs. Furthermore, the bootstrapped drive
allows an external NMOS transistor for the main switch instead
of a PMOS. A boost capacitor of 0.1 μF must be added
externally between BST and SW.
The DRVL pin switches between DRVREG and PGND. The
5.25 V output of DRVREG drives the external NMOS with high
V
GS
to lower the on resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
the SW node to ground. At this point, the boost capacitor is
charged up through the internal boost diode. When the PWM
switches high, DRVL is turned off and DRVH turns on. DRVH
switches between BST and SW. When DRVH is on, the SW pin
is pulled up to the input supply (typically 16 V), and BST rises
above this voltage by approximately 4.75 V.
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3808 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a delay
of 50 ns before turning DRVH on.
When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low-side MOSFET and DRVL
is held low. The DRVLSD threshold is set to 0.8 V correspond-
ing to a 32 mV differential between the CS pins.
The driver stage monitors the voltage across the BST capacitor
with CMP3. When this voltage is less than 4 V, CMP3 forces a
minimum off time of 200 ns. This ensures that the BST capacitor
is charged even during DRVLSD. However, because a minimum
off time is only forced when needed, the maximum duty cycle is
greater than 99%.
SYSTEM CURRENT SENSE
An uncommitted differential amplifier is provided for
additional high-side current sensing. This amplifier, AMP2,
has a fixed gain of 50 V/V from the SYSP and SYSM pins to the
analog output at ISYS. ISYS has a 100 μA source capability to
drive an external load. The common-mode range of the input
pins is from 10 V to 22 V. This amplifier is the only part of the
ADP3808 that remains active during shutdown. The power to
this block is derived from the bias current on the SYSP and
SYSM pins.
相關PDF資料
PDF描述
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相關代理商/技術參數
參數描述
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