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參數資料
| 型號： | ADP3808JCPZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩壓器 |
| 英文描述： | High Efficiency Switch Mode Li-Ion Battery Charger |
| 中文描述： | BATTERY CHARGE CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, QCC24 |
| 封裝： | ROHS COMPLIANT, MO-220VGGD-2, LFCSP-24 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 315K |
| 代理商： | ADP3808JCPZ-RL |
ADP3808
Parameter
OSCILLATOR
Maximum Frequency
Frequency Variation
RT Output Voltage
Zero Duty Cycle Threshold
Maximum Duty Cycle Threshold
LOGIC INPUTS (EN, CELLSEL)
Input Voltage High
Input Voltage Low
Input Current
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Time
Propagation Delay Time
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Time
Propagation Delay Time
3
Timeout Delay
4
Rev. 0 | Page 4 of 16
Symbol
f
OSC
Δ
f
OSC
V
RT
V
IH
V
IL
I
IN
t
rDRVH
, t
fDRVH
t
pdhDRVH
t
rDRVL
, t
fDRVL
t
pdhDRVL
V
CC
I
VCC
I
VCC(SD)
V
UVLO
V
DRVREG
I
DRVREG
Conditions
RT = 150 kΩ
Measured at COMP
Measured at COMP
Inputs = 0 V or 5 V
BST to SW = 5 V
BST to SW = 5 V
BST to SW = 0 V
BST to SW = 5 V, C
LOAD
= 1 nF
BST to SW = 5 V, C
LOAD
= 1 nF
VCC = PGND
C
LOAD
= 1 nF
C
LOAD
= 1 nF
SW = 5 V
SW = PGND
EN = 5 V
EN = 0 V
V
CC
rising
C
L
= 100 nF
Min
250
1.9
2.0
–1
25
150
150
10
9
5.0
10
Typ
1
290
2
1
2
3
3
10
20
60
3.8
1.5
10
20
15
300
300
9.8
5
9.5
600
5.25
Max
340
2.1
0.8
+1
8
8
40
85
8
8
40
35
22
12
10
10
5.5
Unit
MHz
kHz
V
V
V
V
V
μA
Ω
Ω
kΩ
ns
ns
Ω
Ω
kΩ
ns
ns
ns
ns
V
mA
μA
V
mV
V
mA
SUPPLY V
CC
Supply Voltage Range
Supply Current
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
DRV Regulator Output Voltage
DRV Regulator Output Current
1
All limits at temperature extremes are guaranteed via correlation using standard
s
tatistical
q
uality
c
ontrol (SQC) methods.
2
Measured between CSP and CSM. (V
CSP
V
CSM
) = 96 mV × CSADJ/REFIN.
3
For propagation delays, t
pdh
refers to the specified signal going high, and t
pdl
refers to it going low.
4
The turn-on of DRVL is initiated after DRVH turns off by either SW crossing a ~1 V threshold or by expiration of the timeout delay.
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