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參數(shù)資料
型號(hào)： ADSP-21020BG-100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32/40-Bit IEEE Floating-Point DSP Microprocessor
中文描述： 48-BIT, 25 MHz, OTHER DSP, CPGA223
封裝： CERAMIC, PGA-223
文件頁(yè)數(shù)： 10/32頁(yè)
文件大?。?/td> 425K
代理商： ADSP-21020BG-100
ADSP-21020
REV. C
–10–
Table V. Multiplier Compute Operations
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
MRF
MRB
MRxF
MRxB
= Rx * Ry (
S
= Rx * Ry
(
U U I
= Rx * Ry
( U U
FR
= MRF + Rx * Ry (
S
= MRB
+ Rx * Ry (
U U I
= MRF
+ Rx * Ry ( U U
FR
= MRB
= SAT MRF
(
SI
)
= SAT MRB
(
UI
)
= SAT MRF
(
SF
)
= SAT MRB
(
UF
)
= 0
S
F
)
Fn
= Fx * Fy
S
F
)
Rn
Rn
MRF = MRF
= Rx * Ry
(
U U I
FR
MRB = MRB
Rn
= RND MRF
Rn
= RND MRB
MRF = RND MRF
MRB = RND MRB
= MRF
= MRB
= Rx * Ry
(
U U I
– Rx * Ry (
S
S
F
)
(
SF
)
(
UF
)
= Rn
Rn
Rn
=
=
MRxF
MRxB
Rn, Rx, Ry
Fn, Fx, Fy
MRxF
MRxB
( x-input
( x-input
S
U
I
F
FR
(SF)
(SSF)
R15–R0; register file location, fixed-point
F15–F0; register file location, floating-point
MR2F, MR1F; MR0F; multiplier result accumulators, foreground
MR2B, MR1B, MR0B; multiplier result accumulators, background
y-input
data format, )
y-input
rounding
Signed input
Unsigned input
Integer input(s)
Fractional input(s)
Fractional inputs, Rounded output
Default format for 1-input operations
Default format for 2-input operations
Table VI. Shifter and Shifter Immediate Compute Operations
Shifter
Shifter Immediate
Rn = LSHIFT Rx BY Ry
Rn = Rn OR LSHIFT Rx BY Ry
Rn = ASHIFT Rx BY Ry
Rn = Rn OR ASHIFT Rx BY Ry
Rn = ROT Rx BY RY
Rn = BCLR Rx BY Ry
Rn = BSET Rx BY Ry
Rn = BTGL Rx BY Ry
BTST Rx BY Ry
Rn = FDEP Rx BY Ry
Rn = Rn OR FDEP Rx BY Ry
Rn = FDEP Rx BY Ry (SE)
Rn = Rn OR FDEP Rx BY Ry (SE)
Rn = FEXT Rx BY Ry
Rn = FEXT Rx BY Ry (SE)
Rn = EXP Rx
Rn = EXP Rx (EX)
Rn = LEFTZ Rx
Rn = LEFTO Rx
Rn = LSHIFT Rx BY<data8>
Rn = Rn OR LSHIFT Rx BY<data8>
Rn = ASHIFT Rx BY<data8>
Rn = Rn OR ASHIFT Rx BY<data8>
Rn = ROT Rx BY<data8>
Rn = BCLR Rx BY<data8>
Rn = BSET Rx BY<data8>
Rn = BTGL Rx BY<data8>
BTST Rx BY<data8>
Rn = FDEP Rx BY <bit6>: <len6>
Rn = Rn OR FDEP Rx BY <bit6>:<1en6>
Rn = FDEP Rx BY <bit6>:<1en6> (SE)
Rn = Rn OR FDEP Rx BY <bit6>:<1en6> (SE)
Rn = FEXT Rx BY <bit6>:<1en6>
Rn = FEXT Rx BY <bit6>:<1en6> (SE)
Rn, Rx, Ry
<bit6>:<len6> 6-bit immediate bit position and length values (for shifter immediate operations)
R15-R0; register file location, fixed-point
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21020BG-120 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020BG-80 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020KG-100 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020KG-133 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-21020KG-60 制造商:Rochester Electronics LLC 功能描述:- Bulk
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