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參數(shù)資料
型號: ADSP-21065LKS-240
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 32-BIT, 33.33 MHz, OTHER DSP, PQFP208
封裝: MS-029FA-1, MQFP-208
文件頁數(shù): 18/44頁
文件大小: 331K
代理商: ADSP-21065LKS-240
REV. B
ADSP-21065L
–18–
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter
Min
Max
Units
Timing Requirements:
t
SSDATI
t
HSDATI
t
DAAK
t
SACKC
t
HACK
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address,
MS
x,
SW
,
BMS
1, 2
ACK Setup Before CLKIN
1
ACK Hold After CLKIN
0.25 + 2 DT
4.0 – 2 DT
ns
ns
ns
ns
ns
24.0 + 30 DT + W
2.75 + 4 DT
2.0 – 4 DT
Switching Characteristics:
t
DADRO
t
HADRO
t
DRDO
t
DWRO
t
DRWL
t
DDATO
t
DATTR
t
DBM
t
HBM
Address,
MS
x,
BMS
,
SW
Delay After CLKIN
1
Address,
MS
x,
BMS
,
SW
Hold After CLKIN
RD
High Delay After CLKIN
WR
High Delay After CLKIN
RD
/
WR
Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
3
BMSTR Delay After CLKIN
BMSTR Hold After CLKIN
7.0 – 2 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5 – 2 DT
0.5 – 2 DT
0.0 – 3 DT
7.5 + 4 DT
6.0 – 2 DT
6.0 – 3 DT
11.75 + 4 DT
22.0 + 10 DT
7.0 – 2 DT
3.0
1.0 – 2 DT
–4.0
W = (number of wait states specified in WAIT register)
×
t
CK
.
NOTES
1
Data Hold: User must meet t
HDA
or t
HDRH
or synchronous specification t
HDATI
. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.
2
ACK is not sampled on external memory accesses that use the
Internal
wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for wait state modes
External
,
Either
, or
Both
(
Both
, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t
SACKC
and t
HACKC
must be met for wait state modes
External
,
Either
, or
Both
(
Both
, after internal wait states have completed).
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
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