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參數資料
| 型號： | ADSP-21065LKS-240 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 32-BIT, 33.33 MHz, OTHER DSP, PQFP208 |
| 封裝： | MS-029FA-1, MQFP-208 |
| 文件頁數： | 28/44頁 |
| 文件大小： | 331K |
| 代理商： | ADSP-21065LKS-240 |
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REV. B
ADSP-21065L
–28–
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand-
shake mode,
DMAG
controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled
by the ADDR
23-0
,
RD
,
WR
,
SW
,
MS
3-0
, ACK, and
DMAG
signals. Extern mode cannot be used for transfers with SDRAM. For
Paced Master mode, the data transfer is controlled by ADDR
23-0
,
RD
,
WR
,
MS
3-0
, and ACK (not
DMAG
). For Paced Master mode,
the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for
ADDR
23-0
,
RD
,
WR
,
MS
3-0
,
SW
, DATA
31-0
, and ACK also apply.
Parameter
Min
Max
Units
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
DMAR
x Low Setup Before CLKIN
1
DMAR
x High Setup Before CLKIN
1
DMAR
x Width Low (Nonsynchronous)
Data Setup After
DMAG
x Low
2
Data Hold After
DMAG
x High
Data Valid After
DMAR
x High
2
DMAR
x Low Edge to Low Edge
DMAR
x Width High
5.0
5.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
15.0 + 20 DT
0.0
25.0 + 14 DT
18.0 + 14 DT
6.0
Switching Characteristics:
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
DADGH
t
DDGHA
t
VDATDGH
t
DATRDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
DMAG
x Low Delay After CLKIN
DMAG
x High Width
DMAG
x Low Width
DMAG
x High Delay After
CLKIN
Address Select Valid to
DMAG
x High
Address Select Hold After
DMAG
x High
Data Valid Before
DMAG
x High
3
Data Disable After
DMAG
x High
4
WR
Low Before
DMAG
x Low
DMAG
x Low Before
WR
High
WR
High Before
DMAG
x High
RD
Low Before
DMAG
x Low
RD
Low Before
DMAG
x High
RD
High Before
DMAG
x High
DMAG
x High to
WR
,
RD
Low
14.0 + 10 DT
10.0 + 12 DT + HI
16.0 + 20 DT
0.0 – 2 DT
28.0 + 16 DT
–1.0
16.0 + 20 DT
0.0
5.0 + 6 DT
18.0 + 19 DT + W
0.75 + 1 DT
5.0
24.0 + 26 DT + W
0.0
5.0 + 6 DT + HI
20.0 + 10 DT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0 – 2 DT
4.0
8.0 + 6 DT
3.0 + 1 DT
8.0
2.0
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if
DMAR
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the
data can be driven t
DATDRH
after
DMAR
x is brought high.
3
t
VDATDGH
is valid if
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then t
VDATDGH
= 8 + 9 DT + (n
×
t
CK
) where
n
equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
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