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參數(shù)資料
| 型號(hào)： | ADSP-2109LKP-55 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Low Cost DSP Microcomputers |
| 中文描述： | 24-BIT, 13.824 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 20/36頁(yè) |
| 文件大小： | 333K |
| 代理商： | ADSP-2109LKP-55 |
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ADSP-2104/ADSP-2109
–20–
REV. 0
GE NE RAL NOT E S
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
T IMING NOT E S
Switching characteristics
specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
TIMNGPARAMETERS (ADSP-2104/ADSP-2109)
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements
apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. T iming requirements guarantee that the
processor operates correctly with other devices.
ME MORY RE QUIRE ME NT S
T he table below shows common memory device specifications
and the corresponding ADSP-2104/ADSP-2109 timing
parameters, for your convenience.
Memory
Device
Specification
ADSP-2104/ADSP-2109
T iming
Parameter
T iming
Parameter
Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
t
ASW
t
AW
t
WRA
t
DW
t
DH
t
RDD
t
AA
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
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